Post design integrated circuit manufacturing obfuscation
Inventors
Levine, Neal • Gahoonia, Aman • Lloyd, Jon • Pentrack, David W.
Assignees
United States Department of the Army
Publication Number
US-9940419-B1
Publication Date
2018-04-10
Expiration Date
2036-04-27
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Abstract
Integrated circuit design layout files are partitioned into one or more design layout files containing data for Front-End-Of-Line sub-circuits and one or more design layout files containing data for Back-End-Of-Line sub-circuits. By sending each of the files to a separate foundry for manufacture, an intellectual property owner can ensure integrity of his property as no individual file alone contains sufficient information to deduce the overall function of the integrated circuit.
Core Innovation
The invention relates to a method for mitigating the risk of intellectual property theft in integrated circuit manufacturing by partitioning integrated circuit design layout files into multiple design layout files. One or more files contain data for Front-End-Of-Line (FEOL) sub-circuits and one or more files contain data for Back-End-Of-Line (BEOL) sub-circuits. These files are sent to separate foundries for manufacture such that no single file contains sufficient information to deduce the overall function of the integrated circuit.
The problem solved by the invention arises from vulnerabilities in protecting integrated circuit intellectual property during manufacturing. Traditional methods such as circuit obfuscation and staff vetting are limited in effectiveness because adversaries can overcome obfuscation, and human vetting can fail. There is a need for a manufacturing scheme that by design provides no individual foundry enough information to deduce the circuit's function, thereby protecting the confidentiality and integrity of critical integrated circuits in sectors like banking, defense, and civic infrastructure.
The invention achieves risk mitigation by morphing a completed integrated circuit design file into multiple design files where the FEOL sub-circuit layout is separated and each BEOL sub-circuit layout layer is distributed independently. These layers are sent to different foundries, each fabricating separate substrates. After fabrication, these multiple substrates are physically stacked at a specified location to form the complete integrated circuit, ensuring that no individual foundry has access to the entire design functionality.
Claims Coverage
The patent includes two independent claims covering methods for reducing intellectual property theft by partitioning integrated circuit designs into FEOL and BEOL layer files and assembling them, with additional inventive features related to layout morphing, foundry distribution, and assembly.
Partitioning integrated circuit design files into FEOL and BEOL layer files
Dividing the integrated circuit design file into multiple layer files that include at least one front end of line (FEOL) sub-circuit layer file and at least one back end of line (BEOL) sub-circuit layer file.
Morphing contacts and vias into pad patterns for vertical current flow
For each layer file, morphing one or more contacts and vias into pad patterns and creating layout files that redistribute contacts and vias into pad arrays to facilitate vertical current flow between stacked sub-circuits, along with layout files defining vias for electrical connections of the pad arrays to the sub-circuit.
Distributing layer files to different foundries
Providing the FEOL layer files to a first foundry and the BEOL layer files to a different second foundry, ensuring no single foundry receives the complete integrated circuit design.
Assembling sub-circuits into a vertically stacked integrated circuit
Assembling the fabricated FEOL and BEOL sub-circuits into an integrated circuit by vertically stacking them, forming either a three dimensional (3D) or 2.5 dimensional (2.5D) integrated circuit.
Adjusting simulation models to account for partitioned IC architecture
Simulating parameters of the integrated circuit by adjusting interconnect delay simulation models to account for signal transmission delays through vertically stacked sub-circuits.
Retrofitting existing integrated circuit designs with partitioning
A method for retrofitting integrated circuit design files by partitioning them into FEOL and BEOL layer files, morphing contacts and vias, distributing to different foundries, and assembling into integrated circuits, without requiring modification of the original design process.
The independent claims collectively cover methods to protect integrated circuit intellectual property by partitioning traditional IC design files into FEOL and BEOL layers, morphing contact and via layouts for inter-layer connectivity, distributing these partitions to separate foundries for manufacture, and assembling the sub-circuits into a stacked integrated circuit, including retrofitting existing designs and adjusting simulation models for this architecture.
Stated Advantages
Provides significant confidentiality and integrity protection by ensuring no single foundry has sufficient information to deduce the integrated circuit's function.
Allows the circuit designer to use standard design methodologies without modification since partitioning is performed post-design.
Mitigates risks associated with manufacturing sensitive circuits in non-vetted foundries by structural partitioning.
Transforms a single design into multiple layout files, each devoid of algorithmic information, thus preventing trade secret misappropriation.
Documented Applications
Protecting intellectual property in integrated circuits used within critical systems such as financial, national defense, and civic infrastructure.
Manufacturing integrated circuits where distributed fabrication among multiple foundries protects against reverse engineering and unauthorized access.
Assembling vertically stacked integrated circuits via 2.5D or 3D integration following partitioned fabrication.
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