Dynamically addressable master-slave system and method for dynamically addressing slave units
Inventors
Sauer, Thomas • Lipp, Helmut • Teuke, Klaus • Humm, Markus • Fessel, Andreas • Buerkert, Martin
Assignees
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Publication Number
US-9880950-B2
Publication Date
2018-01-30
Expiration Date
Abstract
A master-slave system includes a master unit having a digital output for providing a signal or a serial signal sequence of signals, and at least two slave units. Each of the slave units includes at least one digital serial memory having a size of one bit, and each slave unit includes an input and an output. The slave units are serially connected to one another via the inputs and the outputs via a signal line (5). The output of a first slave unit is connected via the signal line to the digital output of the master unit. The master slave system is configured so that a signal supplied by the digital output is detected at the input of the slave unit, in order to raise the address of the corresponding slave unit in each case by the value “1”, to store the signal change in the memory and to output a signal corresponding to the content of the memory at the output of the memory.
Core Innovation
The invention relates to a dynamically addressable master-slave system with a master unit and at least two serially connected slave units. The master unit has a digital output for supplying a serial signal sequence of signals, and the slave units each include at least one digital serial memory having a size of one bit with an input and an output. The slave units are serially connected to one another via the inputs and the outputs via a signal line, with the input of a first slave unit connected to the digital output of the master unit.
In operation, a signal change of the serial sequence of signals is detected at the input of a first slave unit. In reaction to the signal change, the system raises the address of the corresponding slave unit by the value “1”, stores the signal change in the memory, where only a positive change of flank is stored, and outputs a signal corresponding to the content of the memory at the output of the respective slave unit and thus at the input of the next slave unit. This produces a serial progression in which each slave forwards a signal representing its stored one-bit memory content.
A dynamic addressing procedure is used with an address mode and a lock mode, using address-mode (Sa) and lock-mode (Sp) signals. The procedure includes initializing all slave addresses to a common value and all memories to zero, then detecting completion and returning to a non-signaled state after each signal. Refinements include implementations such as a ring system via a return line from the last slave to the master, and timing-based termination using a maximum time span (tmax) after which addresses and memory values are reset.
Claims Coverage
The claims present one core inventive architecture and multiple refinements. The core inventive features center on serial master-slave dynamic addressing with one-bit memories, positive flank-only storage, and signal forwarding; additional features address topology, mode switching, initialization, termination, and completion detection.
Serial master-slave dynamic addressing via one-bit memories
A master-slave system in which a master unit supplies a serial signal sequence via a digital output to serially connected slave units, where each slave unit includes at least one digital serial memory of one bit with an input and an output, and each slave unit detects a signal change and raises its own slave address by “1” while storing the change.
Positive flank-only storage and forwarding
The system stores only a positive change of flank in the one-bit digital serial memory and outputs a signal corresponding to the content of the memory at the output of each slave unit so that the output is supplied to the input of the next slave unit.
Ring topology with return line to the master
The system provides a ring system via a return line from the last slave to the master unit.
Master implemented as control, computer, or push button
The master unit is implemented as a memory-programmable control, a computer with corresponding hardware interfaces (or not freely programmable control), or a unit having a push button for generating the signal.
Mode switching between lock and address using Sa and Sp
The system switches between lock mode and address mode using an address-mode signal (Sa) and a lock-mode signal (Sp).
Initialization and dynamic addressing procedure with memory cleared to zero
The system begins with initial equal addresses for the slave units and all memories cleared to zero, then performs dynamic addressing by detecting signal changes of the supplied serial signal sequence.
Timing termination with maximum time span tmax and reset
A maximum time span is used so that, if exceeded during a signal change, address assignment is terminated and the memory values and address values are reset to the output value.
Extra signal change for end-of-series completion
The master unit generates one additional signal change beyond the number of slave units so that the last slave unit is raised by one additional address unit via a return line, and the master unit detects the conclusion of the addressing process.
Alternative bus-telegram signaling to a uniquely identified first slave
An alternative design omits direct master-to-first-slave signalling and instead uses bus telegrams to a uniquely identified first slave.
Across the claims, the core inventive concept is a serially connected master-slave system where each slave detects a signal change, increments its address by “1”, stores only positive flank changes in a one-bit digital serial memory, and forwards the memory content onward. Dependent refinements constrain topology, define master implementations and mode switching, and add initialization, termination/reset timing, and completion detection.
Stated Advantages
Not explicitly described in patent.
Documented Applications
Not explicitly described in patent.
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