Resource and core scaling for improving performance of power-constrained multi-core processors
Inventors
Assignees
National Science Foundation NSF • Wisconsin Alumni Research Foundation
Publication Number
US-9606842-B2
Publication Date
2017-03-28
Expiration Date
2033-05-08
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Abstract
A multi-core processor provides circuitry for jointly scaling the number of operating cores and the amount of resources per core in order to maximize processing performance in a power-constrained environment. Such scaling is advantageously provided without the need for scaling voltage and frequency. Selection of the number of operating cores and the amount of resources per core is made by examining the degree of instruction and thread level parallelism available for a given application. Accordingly, performance counters (and other characteristics) implemented in by a processor may be sampled on-line (in real time) and/or performance counters for a given application may be profiled and characterized off-line. As a result, improved processing performance may be achieved despite decreases in core operating voltages and increases in technology process variability over time.
Core Innovation
The invention provides a multi-core processor with circuitry for jointly scaling the number of operating cores and the amount of resources per core in order to maximize processing performance in a power-constrained environment. This scaling is done advantageously without necessity for voltage and frequency scaling, based on examination of the degrees of instruction level parallelism and thread level parallelism available for a given application. Performance counters may be sampled on-line in real time or applications may be profiled off-line to determine optimal configurations.
The problem solved is that modern multi-core processors operate under maximum power budgets, where running all cores and full resources often exceeds the power limit causing failures or damage. Traditional methods dynamically scale voltage and frequency to manage power, but these methods become less feasible with decreased nominal voltages and increased manufacturing process variability. Therefore, there is a need for improved methods to maximize processing performance while meeting power constraints without relying solely on voltage and frequency scaling.
The invention enables processors to selectively enable a number of cores and scale the resources per core independently, such as instruction queues, register files, re-order buffers, load-store queues, caches, and execution units. This selection is made according to measured instruction and thread level parallelism of applications and available power budgets. By exploiting instruction and thread level parallelisms, improved processing performance can be achieved within power constraints and independent of voltage/frequency scaling.
Claims Coverage
The patent includes two independent claims focusing on a processor apparatus and a method for power-constrained processing performance optimization.
Joint core and resource scaling based on parallelism levels
The processor comprises multiple CPU cores with compute resources like caches and execution units, and circuitry to selectively enable cores and scale resources per core independently. The processor determines instruction level parallelism and thread level parallelism by sampling counters such as instructions per cycle and execution time, and disables cores or scales resources accordingly to optimize performance without scaling voltage and frequency.
Method for dynamic core enabling and resource scaling
A method of operating a processor by determining instruction and thread level parallelism from counters indicating instructions per cycle and execution time, selectively enabling cores based on thread level parallelism, and scaling resources within enabled cores based on instruction level parallelism independently from voltage and frequency scaling.
The claims cover a processor and method that dynamically and independently scale the number of enabled cores and compute resources per core according to measured instruction and thread level parallelism, thereby maximizing performance while respecting power constraints without relying on voltage or frequency scaling.
Stated Advantages
Improved processing performance within power constraints by joint and selective scaling of cores and cores' resources.
Elimination of dependency on voltage and frequency scaling, which is becoming less feasible due to manufacturing constraints.
Ability to exploit available instruction level and thread level parallelism dynamically for diverse application workloads.
Flexibility to scale various micro-architectural resources within cores to optimize power efficiency and performance trade-offs.
Documented Applications
Multi-core processors executing one or more applications with varying instruction and thread level parallelism under a maximum power budget.
Processors in power-constrained environments such as mobile, desktop, or server systems having multiple CPU cores where performance and power management are critical.
Runtime systems that utilize performance counters to dynamically adjust core and resource configurations based on current application characteristics.
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