Memory controller for heterogeneous computer
Inventors
Assignees
National Science Foundation NSF
Publication Number
US-9501227-B2
Publication Date
2016-11-22
Expiration Date
2034-08-21
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Abstract
A memory controller for heterogeneous computer processors dynamically adjusts access priorities by the different processors to maximize performance in the execution of a single parallel application program on both processor architectures. In one embodiment, the memory controller predicts sequential memory accesses by the processor having higher memory latency or fewer access requests to lockout the other processor during those sequences for improved implementation of the intended prioritization.
Core Innovation
The invention provides a memory controller for heterogeneous computer processors that dynamically adjusts access priorities between different processors to maximize performance in executing a single parallel application program on both processor architectures. It includes a priority value adjuster that measures the execution time of a single parallel application running on both the first and second processors and adjusts the priority value to minimize the longest execution time of the portions. This adjustment is dynamic and occurs during runtime.
The memory controller prevents high-priority memory access requests from the first processor, which has higher sensitivity to memory latency or fewer access requests, from being blocked behind more frequent but lower priority requests from the second processor. It achieves this by implementing a memory access lockout that locks out memory access requests from the second processor to a portion of memory for an adjustable lockout period after a memory access request from the first processor to that portion. The lockout period is dynamically adjusted based on measurements of sequential memory access patterns, improving the implementation of intended prioritization.
In one embodiment, this system applies a priority threshold to random numbers to enable multivalue priority in hardware, and the lockout period can be controlled independently for different memory banks, reflecting their ability to serve memory requests independently. The invention complements program allocators that distribute portions of a single parallel application between the heterogeneous processors, thus achieving improved execution by better managing memory access contention.
Claims Coverage
The patent includes one independent claim that defines the core inventive features of the heterogeneous computer memory controller with dynamic priority adjustment and lockout mechanisms.
Dynamic priority adjustment to minimize execution time
A memory controller giving a changing level of priority to memory access requests from a first processor using a multivalue priority value, where a priority value adjuster measures execution times of portions of a single parallel application on both processors and adjusts the priority value to minimize the longest execution time of those portions during execution.
Memory access lockout based on sequential access patterns
A memory access lockout feature that locks out memory access requests from the second processor to a portion of the memory for a predetermined lockout period after a memory access request from the first processor to that portion, thereby preventing lower priority requests from defeating prioritization by volume.
The claims cover a heterogeneous computer system with mechanisms for dynamic, multilevel priority adjustment based on execution time measurements and a lockout mechanism for memory access to preserve priority and improve execution time of single parallel applications.
Stated Advantages
Improved execution of single parallel programs in a heterogeneous environment.
Enhanced memory access prioritization in common heterogeneous computers having a CPU and a GPU.
Prevention of high-frequency memory access requests from one processor from defeating prioritization of another processor with fewer requests.
Provision of a flexible and dynamically adjustable lockout window to adapt to changing program behavior.
Prediction and adjustment of lockout timing for efficient priority enforcement without unnecessary delays.
Independent lockout control for separate memory banks that can operate without access conflicts.
Implementation that can partly reside as software programs running on existing processors, easing deployment.
Capability to complement program allocation strategies to optimize load balancing between heterogeneous processors.
A simple hardware viable approach using a random number threshold to implement multivalued priority.
Support for execution of single parallel applications where portions are interdependent across heterogeneous processors.
Documented Applications
Execution of single parallel application programs divided among heterogeneous processors such as CPUs and GPUs with shared memory.
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