Floating point multiply-add-substract implementation
Inventors
Assignees
US Department of Navy • Government of the United States of America
Publication Number
US-9417839-B1
Publication Date
2016-08-16
Expiration Date
2034-11-07
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Abstract
A floating point multiply and addition/subtraction implementation is provided. Two operands are received in a standard floating point format with a code selecting a mathematic operation from addition, subtraction, and multiplication. Result mantissas and exponents are calculated simultaneously for all operations. The implementation simplifies computation of a result mantissa by dropping the least significant bits of the operands before computing the result. Underflow and overflow errors are shown by two extra bits in the exponent portion of the result. The mantissa result and the exponent result are selected by providing the operation code to a mantissa multiplexer and an exponent multiplexer. The selected mantissa and exponent are combined as output.
Core Innovation
The invention provides an implementation of a floating point multiply and addition/subtraction unit for digital circuitry that processes two operands in a standard floating point format with a user-supplied code selecting the mathematical operation from addition, subtraction, and multiplication. The result mantissas and exponents are calculated simultaneously for all operations, and the implementation simplifies the computation of a result mantissa by dropping the least significant bits of the operands before computing the result.
The implementation handles underflow and overflow errors by adding two extra bits in the exponent portion of the result. The mantissa and exponent results are selected based on the operation code through respective multiplexers, and then combined to form the output. This system uses signed two's complement format for the exponent with two extra bits to simplify exception handling, eliminating complex detection circuitry by easy error identification through the two most significant bits of the exponent.
Claims Coverage
The patent contains one independent claim detailing the apparatus structure for computing floating point operations, presenting multiple inventive features.
Floating point multiply-add-subtract apparatus with simultaneous exponent and mantissa processing
The apparatus computes multiplication, addition, or subtraction of two floating point operands using a user-supplied opcode, receiving mantissas and exponents, calculating multiplication mantissa product and exponent sum with at least one extra exponent bit, and providing a multiplication output sign via XOR of operand signs.
Exponent and mantissa alignment with scaling for addition and subtraction
An addition/subtraction exponent comparator and subtractor calculate the greater exponent and scale difference. A register aligns mantissas according to the scale difference, providing them to an adder/subtractor for signed addition and subtraction results.
Multiplexing of exponent and mantissa outputs based on opcode
Exponent and mantissa multiplexers select the appropriate result exponent and mantissa based on the opcode, choosing between multiplication and addition/subtraction preliminary results for exponent, and among signed multiplication, addition, or subtraction results for mantissa.
Error detection based on additional exponent bits
An error detector monitors the two most significant bits of the result exponent to indicate error conditions if asserted, providing an error condition indicator output along with the result exponent and mantissa.
These inventive features combine to allow a single floating point unit apparatus capable of multiply, add, and subtract operations with simplified exception detection and precision management utilizing additional exponent bits, aligned mantissa processing, and opcode-based multiplexing for results.
Stated Advantages
Reduces gate count needed for floating point operations, enabling implementations with fewer hardware resources.
Enables faster operation speeds compared to existing floating point units by simplifying computation and exception handling.
Simplifies exception detection hardware by using two extra bits in exponent for underflow, overflow, and NaN identification.
Documented Applications
Implementation in field programmable gate arrays and specialized semiconductors where reduced gate count and faster speed for floating point processing is desirable.
High speed floating point units for digital computing requiring multiply, add, and subtract capabilities with simplified hardware complexity.
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