Self-modifying FPGA for anti-tamper applications
Inventors
Lewis, James M. • Haddock, Joey R. • Walther, Dane R.
Assignees
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Publication Number
US-8896346-B1
Publication Date
2014-11-25
Expiration Date
Abstract
A self-modifying FPGA system includes an FPGA and a configuration memory coupled to the FPGA for providing the FPGA with configuration data including SAFE configuration data and dormant configuration data. The SAFE configuration data is initially loaded to the FPGA and the FPGA is configured to a safe operating mode. Upon a determination to proceed to a next step of self modification, dormant configuration data contained in the configuration memory is loaded into the FPGA and the FPGA is configured to a secure operating mode.
Core Innovation
An anti-tamper self-modifying SRAM-FPGA system is described in which an FPGA includes a configuration memory coupled to provide configuration data including SAFE configuration data and dormant configuration data. The configuration memory includes a PROM and SRAM, and the system initially loads the SAFE configuration data to configure the FPGA into a safe operating mode.
After a determination to proceed to a next step of self modification, dormant configuration data contained in the configuration memory is loaded into the FPGA and the FPGA is configured to a secure operating mode. The SAFE configuration data includes user mode logic functionality to read data from the PROM and write data to the SRAM appropriately to transfer dormant configuration data contained within the PROM to the SRAM.
The description further includes an architecture in which dormant configuration data is transferred into SRAM and the FPGA reconfigures into the secure operating mode. It also describes sanitization of SRAM by clearing or removing traces and reverting to SAFE on reset or shutdown, and multiple dormant data sets.
Claims Coverage
The independent claim coverage centers on one self-modifying FPGA system with configuration memory including PROM and SRAM, SAFE configuration data and dormant configuration data, and a SAFE-to-secure reconfiguration flow controlled by a determination to proceed.
Safe operating mode followed by secure operating mode self modification
SAFE configuration data is initially loaded so the FPGA is configured to a safe operating mode, and upon a determination to proceed to a next step of self modification, dormant configuration data is loaded and the FPGA is configured to a secure operating mode.
PROM-to-SRAM transfer of dormant configuration data using user mode logic
SAFE configuration data includes user mode logic functionality to read data from the PROM and write data to the SRAM appropriately to transfer dormant configuration data contained within the PROM to the SRAM.
Configuration memory including PROM and SRAM for providing configuration data
A configuration memory coupled to the FPGA provides configuration data including SAFE configuration data and dormant configuration data, where the configuration memory includes a PROM and SRAM.
Independent claim coverage centers on a self-modifying FPGA that starts in a safe operating mode using SAFE configuration data, then loads dormant configuration data and switches to a secure operating mode, with SAFE configuration data using user mode logic to transfer dormant configuration data from PROM to SRAM.
Stated Advantages
Not explicitly described in patent.
Documented Applications
Not explicitly described in patent.
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