Logical slot to distributed hardware slot scheduling for graphics work
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Assignees
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Publication Number
US-12737829-B2
Publication Date
2026-09-15
Expiration Date
Abstract
Disclosed techniques relate to assigning graphic work from logical slots of graphics control circuitry to distributed hardware slots of graphics processor sub-units. In some embodiments, control circuitry assigns respective portions of a set of graphics work from a logical slot to distributed hardware slots based on control information for the set of graphics work. When a full number of distributed hardware slots to be utilized by the set of graphics work are not available, control circuitry may assign a proper sub-set of portions of the set of graphics work to available distributed hardware slots. Control circuitry may support allocating any determined integer number of graphics processor sub-units in a range from one processor sub-unit to a total number of processor sub-units included in the apparatus.
Core Innovation
The disclosure describes implementing a plurality of logical slots for a set of graphics work and executing respective portions of the set by assigning them from logical slots to distributed hardware slots across graphics processor sub-units, including at least a first graphics processor sub-unit and a second graphics processor sub-unit. Each sub-unit implements at least a distributed hardware slot and corresponding shader circuitry for executing the assigned portion.
Control circuitry determines a target number of distributed hardware slots to be utilized for the set of graphics work based on control information. When the target number is greater than a number of available distributed hardware slots, a first proper sub-set is assigned while a first distributed hardware slot is available, and a second proper sub-set is assigned when a second distributed hardware slot becomes available.
The assigned first and second proper sub-sets are stored in work queue circuitry for their respective distributed hardware slots, and configuration registers for the distributed hardware slots are programmed to support execution by first shader circuitry of the first graphics processor sub-unit and by second shader circuitry of the second graphics processor sub-unit. The disclosure further describes slot state management, queue and slot tracking, configuration for distributed-slot execution, and runtime tracking and completion buffers for the distributed processing.
Claims Coverage
The independent claims are clm-00001, clm-00015, and clm-00018, each focusing on logical slots mapped to distributed hardware slots across first and second graphics processor sub-units, with determination of a target number of distributed hardware slots from control information and assignment of proper sub-sets when distributed slots are available.
Logical slot mapping to distributed hardware slots across processor sub-units
Graphics control circuitry implements a plurality of logical slots, and a first graphics processor sub-unit and a second graphics processor sub-unit implement at least first and second distributed hardware slots; control circuitry assigns respective portions of the set of graphics work from a logical slot to at least the first and second distributed hardware slots for execution.
Target slot determination based on control information and ordered subset assignment
Control circuitry determines a target number of distributed hardware slots to be utilized for a set of graphics work based on control information, assigns a first proper sub-set to the first distributed hardware slot in response to the target number being greater than a number of available distributed hardware slots but the first distributed hardware slot being available, and assigns a second proper sub-set to the second distributed hardware slot when the second distributed hardware slot has become available, wherein the assignment of the first proper sub-set is prior to assignment of the second proper sub-set.
Work queue storage and configuration register programming for shader execution
Assignment of the first proper sub-set stores the first portion of the set of graphics work in work queue circuitry for the first distributed hardware slot and programs configuration registers for the first distributed hardware slot to support execution of the first portion by first shader circuitry of the first graphics processor sub-unit; assignment of the second proper sub-set stores the second portion in work queue circuitry for the second distributed hardware slot and programs configuration registers for the second distributed hardware slot to support execution by second shader circuitry of the second graphics processor sub-unit.
Non-transitory medium storing design information for integrated circuit including logical and distributed slot execution
A non-transitory computer readable storage medium having stored design information that specifies a design of at least a portion of a hardware integrated circuit for a semiconductor fabrication system, wherein the design includes graphics control circuitry configured to implement logical slots, first and second graphics processor sub-units configured to implement distributed hardware slots, and control circuitry that determines a target number of distributed hardware slots based on control information and assigns respective portions to first and second distributed hardware slots with ordered proper sub-set assignment.
Method of determining target distributed slots and assigning proper subsets with shader support
A method determines a target number of distributed hardware slots to be utilized for a set of graphics work based on control information, assigns respective portions of the set from a logical slot to at least first and second distributed hardware slots by assigning a first proper sub-set in response to the target number being greater than available distributed hardware slots but the first distributed hardware slot being available, and assigning a second proper sub-set when the second distributed hardware slot has become available, with first prior to second; the method stores assigned portions in work queue circuitry and programs configuration registers to support execution by first and second shader circuitry.
Across clm-00001, clm-00015, and clm-00018, the core claim coverage centers on determining a target number of distributed hardware slots from control information for a set of graphics work, assigning ordered proper sub-sets from a logical slot to available distributed hardware slots across first and second graphics processor sub-units, and storing assigned portions in work queue circuitry while programming configuration registers for shader circuitry execution.
Stated Advantages
Documented Applications
Not explicitly described in patent.
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