Scalable system on a chip
Inventors
Hammarlund, Per H. • Zimet, Lior • Vash, James • Garg, Gaurav • Kolor, Sergio • Kaushikkar, Harshavardhan • Gunna, Ramesh B. • Hutsell, Steven R.
Assignees
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Publication Number
US-12737296-B2
Publication Date
2026-09-15
Expiration Date
Abstract
A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.
Core Innovation
The invention describes a system on a chip (SOC) integrated onto one or more co-packaged semiconductor dies with a unified memory architecture that allows processor cores, graphics processing units, peripheral devices, and a plurality of memory controller circuits to communicate over an interconnect fabric via a unified address space. Adjacent blocks of a given page within the unified address space are distributed among the plurality of memory controller circuits for storage in memory. The SOC provides communication between these components and unifies memory access among them.
The unified memory architecture includes the processor cores, the graphics processing units, the peripheral devices, the memory controller circuits, and the interconnect fabric in the SOC, and multiple SOC components can access any address in the unified address space. Scaling is described using unified address semantics across single- or multi-die systems, including die-to-die transparent interconnect. The interconnect fabric uses multiple physically and logically independent networks with heterogeneous properties, including a coherent CPU I/O network and a relaxed-order non-coherent GPU/network.
To enable coherency over the unified address space, the invention describes a scalable distributed directory-based cache coherency mechanism. Directory distribution is described to the memory controllers, together with coherent transfer signaling using a 3-hop or 4-hop protocol, snoop forward and snoop back messaging, primary shared state and secondary shared state, and expected-state-based race handling for concurrent transactions.
Claims Coverage
The independent claims define two main inventive features.
Unified memory architecture distributing adjacent page blocks among memory controllers in an SOC
A system in which processor cores, graphics processing units, peripheral devices distinct from the processor cores and the graphics processing units, and a plurality of memory controller circuits communicate via a unified memory architecture over an interconnect fabric, where adjacent blocks of a given page within a unified address space are distributed among the plurality of memory controller circuits for storage, and where the processor cores, graphics processing units, peripheral devices, memory controller circuits, and interconnect fabric are included in a system on a chip (SOC) integrated onto one or more co-packaged semiconductor dies.
Method communicating via unified memory architecture and distributing adjacent page blocks among memory controllers in an SOC
A method that communicates, via a unified memory architecture, among a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral devices distinct from the plurality of processor cores and the plurality of graphics processing units, and a plurality of memory controller circuits over an interconnect fabric in a system including an SOC integrated onto one or more co-packaged semiconductor dies, and that distributes, in the SOC, adjacent blocks of a given page within a unified address space defined by the unified memory architecture among the plurality of memory controller circuits for storage in memory.
The claims are directed to an SOC-level unified memory architecture in which heterogeneous agents communicate over an interconnect fabric and adjacent blocks of a given page in a unified address space are distributed among multiple memory controller circuits. The claim set also indicates distributed directory-based coherency features and coherent transfer signaling over the unified address space.
Stated Advantages
Scalable unified address semantics for single- or multi-die systems.
Scalable distributed directory-based cache coherency mechanism over the unified address space.
Supports coherent transfer and snoop forward/snoop back messaging across the unified address space.
Documented Applications
Implemented as a system on a chip (SOC) integrated onto one or more co-packaged semiconductor dies.
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