Integrated memory system for high performance Bayesian and classical inference of neural networks
Inventors
TRIVEDI, Amit Ranjan • Tulabandhula, Theja • SHUKLA, Priyesh • SHYLENDRA, Ahish • NASRIN, Shamma
Assignees
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Publication Number
US-12585927-B2
Publication Date
2026-03-24
Expiration Date
Abstract
A memory module system for a high-dimensional weight space neural network configured to process machine learning data streams using Bayesian Inference and/or Classical Inference is set forth. The memory module can include embedded high speed random number generators (RNGs). The memory module is configured to compute, store and sample neural network weights by adapting operating precision to optimize the computing effort based on available weight space and application specifications.
Core Innovation
The invention relates to an edge-implementable integrated memory module system for a high-dimensional weight space neural network configured to process machine learning data streams. The memory module includes a static random access memory (SRAM) array and a cross-SRAM processing layer that co-locates statistical density storage, weight sampling, and scalar product computation.
The memory module embeds random number generators within the memory module and stores neural network weights. It is configured to sample the neural network weights and compute one or more scalar product using the sampled neural network weights and corresponding applied inputs, and it transforms one or more scalar products into an output signal.
The described system employs mixed-signal peripherals for current-mode scalar product computation and addresses non-idealities associated with SRAM and peripherals by current-mode operation and self-referencing/self-calibration mechanisms. It further includes current-controlled oscillator-based ADC operation and modulated reference-current digital-to-analog converter behavior.
The document also describes an integrated memory array approach that maps Gaussian mixture model density computations onto an integrated memory array within the edge processing device, while executing scalar-product computation within the SRAM and cross-SRAM processing layer. It supports Bayesian inference weight sampling using Markov chain Monte Carlo, including acceptance/rejection based on ratios of Gaussian mixture model density values.
Claims Coverage
The independent claim is directed to an SRAM array with a cross-SRAM processing layer that embeds random number generators to store and sample neural network weights, perform scalar product computation, adapt operating precision, and convert the scalar products into an output signal. The claim set includes 9 inventive features.
Memory module system with SRAM array and cross-SRAM processing layer for scalar products
A memory module comprising a static random access memory (SRAM) array and a cross-SRAM processing layer, where the SRAM array comprises an array of SRAM cells, multiplexer, analog-to-digital converter (ADC) and multiplicand buffer, and where the memory module is configured for scalar product computation to determine statistical density storage.
Embedded random number generators for sampling neural network weights
The memory module with embedded random number generators (RNGs) within the memory module, where the memory module is configured to store neural network weights and sample the neural network weights.
Adaptive operating precision for scalar product computing effort
The memory module configured to compute one or more scalar product using the sampled neural network weights and one or more corresponding applied inputs, where the memory module adapts operating precision to optimize computing effort based on available weight space and application specifications.
Transformation of scalar products into an output signal
Transforming the one or more scalar product into an output signal.
Scalar product port
The memory module system of claim 1 includes at least one scalar product port.
Edge processing device incorporation
The memory module system of claim 1 is incorporated into an edge processing device.
Peripheral DAC driven by row current as current-mode AND gate
A peripheral digital-to-analog converter (DAC) connected to the multiplicand buffer and to a row current of the SRAM array, where the row current provides a current-mode AND gate for the DAC path.
Mapping GMM density computations onto the SRAM array
Gaussian mixture model (GMM) density computations are mapped onto the SRAM array.
Mapping GMM density computations onto an integrated memory array (IMA)
Gaussian mixture model (GMM) density computations are mapped onto an integrated memory array (IMA) of the edge processing device.
Overall, the claim set covers an SRAM-based memory module with a cross-SRAM processing layer and embedded random number generators for sampling neural network weights, performing scalar product computation, adapting operating precision, and converting scalar products into an output signal. Dependent claims further add an interface or port, an edge-device deployment context, a current-mode DAC connection via row current as a current-mode AND gate, and mapping of GMM density computations onto the SRAM array and onto an integrated memory array within the edge processing device.
Stated Advantages
Optimize computing effort by adapting operating precision based on available weight space and application specifications.
Reduce operand movement by performing GMM density computations and exponent computations within the memory.
Documented Applications
Process machine learning data streams using a high-dimensional weight space neural network in an edge processing device.
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