Charge-domain in-memory computing circuit
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Publication Number
US-12524207-B2
Publication Date
2026-01-13
Expiration Date
Abstract
A charge-domain IMC circuit is disclosed and includes: a cluster of 6T SRAM cells; a charge-domain MAC circuit; and an LBL connected to a bit-line of each of the 6T SRAM cells. The MAC circuit includes: a MOS transistor; an input switch; an output switch; an input port; an output port; and a capacitor. The LBL is connected to a gate of the MOS transistor. A first terminal of the MOS transistor is connected to a DC voltage, and a second terminal of the MOS transistor is connected to the output port via the output switch. The second terminal of the MOS transistor is connected to the input port via the input switch and to a first side of the capacitor. A second side of the capacitor is grounded. Other variants of the IMC circuit are disclosed, some of which having a ciSAR ADC or a TD-ADC.
Core Innovation
The invention relates to a charge-domain in-memory computing (IMC) circuit that uses a cluster of a plurality of six-transistor (6T) static random-access memory (SRAM) cells together with a charge-domain multiply-and-accumulate computing (MAC) circuit. A local bit-line (LBL) is connected to a bit-line of each of the 6T SRAM cells, and the LBL is connected to a gate of a MOS transistor. The MOS transistor provides a routing path between an input port and an output port through a capacitor with a capacitor node structure, including a grounded capacitor node in the described configuration.
The MAC circuit includes a MOS transistor, an input switch, an output switch, an input port, an output port, and a capacitor, with DC voltage connected to a first terminal of the MOS transistor. In the configuration where the capacitor second side is grounded, the MOS transistor second terminal is connected to the input port via the input switch and the MOS transistor second terminal is connected to a first side of the capacitor. Dependent configurations additionally introduce an output-line path including a reset switch connected to the output port, and introduce pre-charge and read/write switching to connect a global bit-line (GBL) to the LBL.
The described architecture supports different ADC integrations and MAC operation phases within the charge-domain framework, including TD-ADC implemented as (RO+VTC+TDC) and ciSAR ADC. The document further describes MAC phases such as pre-charge, DAC conversion, multiplication, accumulation, and an optional starting-voltage adjustment, as well as weight encodings including 2’s complement encoding and ternary encoding, and single-ended and differential modes.
Claims Coverage
The partial content includes three independent claims, each covering a charge-domain in-memory computing (IMC) circuit with a 6T SRAM cell cluster and a charge-domain MAC circuit connected through a local bit-line (LBL) and a MOS-transistor/capacitor front-end.
Charge-domain IMC circuit with 6T SRAM cluster and LBL-to-MOS-capacitor MAC
A charge-domain in-memory computing (IMC) circuit comprising a cluster of a plurality of six-transistor (6T) static random-access memory (SRAM) cells, a charge-domain multiply-and-accumulate computing (MAC) circuit, and a local bit-line (LBL), wherein the LBL is connected to a bit-line of each of the 6T SRAM cells, wherein the MAC circuit comprises a metal-oxide-semiconductor (MOS) transistor, an input switch, an output switch, an input port, an output port, and a capacitor, wherein the LBL is connected to a gate of the MOS transistor, wherein a first terminal of the MOS transistor is connected to a DC voltage, and wherein the second terminal of the MOS transistor is connected to the output port via the output switch, the input port via the input switch, and a first side of the capacitor, with a second side of the capacitor grounded.
Charge-domain IMC circuit with LBL-to-MOS-capacitor MAC and output-port-connected capacitor side
A charge-domain in-memory computing (IMC) circuit comprising a cluster of a plurality of six-transistor (6T) static random-access memory (SRAM) cells, a charge-domain multiply-and-accumulate computing (MAC) circuit, and a local bit-line (LBL), wherein the LBL is connected to a bit-line of each of the 6T SRAM cells, wherein the MAC circuit comprises a metal-oxide-semiconductor (MOS) transistor, an input switch, an input port, an output port, and capacitor, wherein the LBL is connected to a gate of the MOS transistor, wherein a first terminal of the MOS transistor is connected to a DC voltage, and wherein a second terminal of the MOS transistor is connected to a first side of the capacitor and to the input port via the input switch, with a second side of the capacitor connected to the output port.
Charge-domain IMC circuit with input-port-connected MOS and output-port-connected capacitor via MOS front-end
A charge-domain in-memory computing (IMC) circuit comprising a cluster of a plurality of six-transistor (6T) static random-access memory (SRAM) cells, a charge-domain multiply-and-accumulate computing (MAC) circuit, and a local bit-line (LBL), wherein the LBL is connected to a bit-line of each of the 6T SRAM cells, wherein the MAC circuit comprises a metal-oxide-semiconductor (MOS) transistor, an input port, an output port, and a capacitor, wherein the LBL is connected to a gate of the MOS transistor, wherein a first terminal of the MOS transistor is connected to the input port, a second terminal of the MOS transistor is connected to a first side of the capacitor, and a second side of the capacitor is connected to the output port.
Across the independent claims, the core claim coverage is directed to a charge-domain IMC circuit using a 6T SRAM cell cluster with a local bit-line (LBL) tied to a MOS transistor gate, and using a capacitor-based charge-domain MAC front-end with defined connections to DC voltage, input port, output port, and, in some configurations, a grounded capacitor node or an output-port-connected capacitor side.
Stated Advantages
Area/energy/throughput advantages.
No energy-hungry references/drivers.
Constant capacitive input impedance enabling buffer-less current-steering DAC.
Documented Applications
MAC and ADC integration, including TD-ADC implemented as (RO+VTC+TDC) and ciSAR ADC, for charge-domain IMC operation supporting CNN weight encodings (2’s complement and ternary) and single-ended/differential modes.
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