System, method, and computer-accessible medium for register-transfer level locking against an untrusted foundry

Inventors

Karri, Ramesh • Garg, Siddharth • PILATO, Christian

Assignees

Politecnico di Milano • New York University

Abstract

Exemplary system, method, and computer-accessible medium for protecting at least one integrated circuit (IC) design, includes generating an abstract syntax tree (“AST”) based on a hardware description language and a first register-transfer level (RTL) design. The method also includes selecting semantic elements in the AST to lock and locking the selected semantic elements. Additionally, the method includes a procedure for generating a second RTL design.

Core Innovation

The problem addressed is protecting integrated circuit (IC) design against an untrusted foundry by performing register-transfer level (RTL) locking of IC IP. The disclosure describes an ASSURE system that locks semantic elements in an IC design at the RTL based on selecting elements from an abstract syntax tree (AST) derived from an input hardware description language (HDL). The locked design is represented as a second RTL design whose functionality matches the original only when a predetermined locking key is applied to the second RTL design.

ASSURE generates an opaque predicate that is performed in hardware, and obfuscates the locked semantic elements with an input key. The technique uses AST-based selection and locking of semantic elements, including constant obfuscation, operation obfuscation, and branch obfuscation, so that the resulting second RTL design exhibits functionality matching conditioned on application of the predetermined locking key. The approach is also described as using an oracle-less threat model and provides mathematical/provable indistinguishability security arguments.

To control which parts of the design are processed for locking, the disclosure describes a blacklist-based module exclusion approach, including excluding reset processes and loop induction variables and other reset-related constants to avoid synthesis/execution issues. The disclosure further describes key-bit budgeting, depth-first analysis, and procedures such as obfuscating selected semantic elements using hardware opaque predicates, while reporting correctness and key-effect metrics. Experimental validation is described using a Verilog/Pyverilog implementation and synthesis with reported area overhead and timing overhead across multiple benchmark suites.

Claims Coverage

The document includes three independent claims: a method claim, a system claim, and a non-transitory computer-accessible medium claim. Across these independent claims, the coverage centers on parsing an input RTL HDL into an abstract syntax tree, selecting semantic elements to lock them via an opaque predicate performed in hardware, obfuscating the locked semantic elements with an input key, and generating a second RTL design whose functionality matches the first when a predetermined locking key is applied. Additional inventive features are described in the dependent claims for key application, selection scope, and predicate characterization.

Across the independent claims, the core inventive coverage consists of parsing input RTL HDL into an abstract syntax tree, selecting semantic elements to lock, performing the locking using a hardware opaque predicate, obfuscating locked semantic elements with an input key, and generating a second RTL design that matches the original functionality only when the predetermined locking key is applied. Dependent claim refinements mentioned in the partial content further characterize selection and key/locking constraints.

Stated Advantages

Documented Applications