Circular buffering in neural network processor

Inventors

Mills, Christopher L.

Assignees

Apple Inc

Abstract

Embodiments of the present disclosure relate to circular buffers in a neural processor circuit. The neural processor circuit includes multiple neural engine circuits and a data processor circuit coupled to at least one of the neural engine circuits. The at least one neural engine circuit performs at least convolution operations. The data processor circuit includes a circular buffer, and a flow control circuit coupled to the circular buffer. The flow control circuit generates at least one addressing parameter that defines wrapping of data in the circular buffer. The circular buffer controls data flow in the neural processor circuit by storing first data associated with the at least one neural engine circuit so that the first data is wrapped around in the circular buffer. An addressing layout of the first data wrapped around in the circular buffer is defined by the at least one addressing parameter.

Core Innovation

The invention describes a neural processor circuit that includes a plurality of neural engine circuits, where at least one neural engine circuit performs convolution operations. A data processor circuit is coupled to the at least one neural engine circuit and includes a circular buffer and a flow control circuit. The flow control circuit generates a plurality of addressing parameters that defines wrapping of data in the circular buffer so that first data is wrapped around in the circular buffer while controlling data flow in the neural processor circuit.

The addressing parameters include a first addressing parameter that determines a start address in the circular buffer for storing the first data. The addressing parameters also include a second addressing parameter that determines an end address of a first segment of the first data in the circular buffer and a start address of a second segment of the first data in the circular buffer. The second segment follows the first segment within the first data, and the second segment precedes the first segment within the circular buffer.

The invention further covers operation of the neural processor circuit where convolution operations are performed by the at least one neural engine circuit while generating addressing parameters that define wrapping of data in a circular buffer of the data processor circuit. A planar engine circuit is coupled to the data processor circuit, and the method updates the plurality of addressing parameters and controls data flow between the neural engine circuit and the planar engine circuit by storing second data in the circular buffer with the updated wrapped addressing layout.

Additionally, an electronic device is described that includes system memory and a neural processor circuit coupled to the system memory, where a memory access operation circuit includes a first circular buffer and a second circular buffer and uses the flow control circuit to generate addressing parameters that define wrapping of data for controlling data flow between the neural processor circuit and the system memory.

Claims Coverage

This document includes three independent claims. Across these independent claims, the inventive concept is expressed using generating addressing parameters to define wrapped addressing layouts in one or more circular buffers, including segment-based start/end addressing and controlling data flow between convolution-capable neural engines, a planar engine circuit, and system memory via a memory access operation circuit.

The independent claims consistently require a flow control circuit that generates addressing parameters to define wrapped addressing layouts for data stored in circular buffers. The claims further specify segment-based start/end addressing for circular wrap-around, include an operating mode where addressing parameters are updated for channel-basis planar engine interactions, and, in the electronic device claim, extend wrapping to data movement between the neural processor circuit and system memory using a memory access operation circuit with first and second circular buffers.

Stated Advantages

Documented Applications