Optimizing space and time of operations for register configurations
Inventors
Assignees
Charles Stark Draper Laboratory Inc
Publication Number
US-12339772-B1
Publication Date
2025-06-24
Expiration Date
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Abstract
Presented herein are systems and methods for configuring devices with write operations. One or more processors can identify a first sequence of write operations to configure a device. Each write operation in the first sequence of write operations can identify a set of a value and an address to which to write the value. The one or more processors can determine one or more distances between a set of the value and the address of a write operation and at least one other set of the value and the address of one or more other write operations in the first sequence of write operations. The one or more processors can generate a second sequence of write operations based at least on the one or more distances. The one or more processors can cause the device to be configured using the second sequence of write operations.
Core Innovation
Presented herein are systems and methods for configuring devices with write operations. One or more processors can identify a first sequence of write operations to configure a device, determine one or more distances between a set of the value and the address of a write operation and at least one other set of the value and the address of one or more other write operations in the first sequence of write operations, generate a second sequence of write operations based at least on the one or more distances, and cause the device to be configured using the second sequence of write operations. In some embodiments the one or more processors can remove redundant write operations, generate a mapping identifying indexed values for unique values, assign indexed addresses, and apply encodings such as ULEB and Huffman to a configuration dataset to be provided to registers.
The background identifies that some computing hardware may entail a significant number of write operations to configure the hardware, that the data used in those writes may take up precious storage in certain small systems, and that many write operations may take time to execute during startup. To address these technical challenges the disclosure optimizes both space taken by the configuration data and time to write configuration data while factoring in constraints on hardware and avoiding very complicated compression schemes. The solution includes reordering tuples of register store operations to minimize a distance metric between tuples, eliding redundant stores, indexing values and addresses to reduce bit-width, and applying simpler encodings and hardware-supported lookups to produce a compact configuration stream readable by hardware or software.
Claims Coverage
Independent claims recite three inventive forms: a method, a system, and a non-transitory computer readable medium. There are 3 inventive features corresponding to those independent claims.
Identifying a first sequence of write operations to configure a device
identifying, by one or more processors, a first sequence of write operations to configure a device, each write operation in the first sequence of write operations identifying a set of a value and an address to which to write the value;
Determining distances and generating a second sequence of write operations
determining, by the one or more processors, one or more distances between a set of the value and the address of a write operation and at least one other set of the value and the address of one or more other write operations in the first sequence of write operations; and generating, by the one or more processors, a second sequence of write operations based at least on the one or more distances;
Causing configuration using the second sequence
causing, by the one or more processors, the device to be configured using the second sequence of write operations;
System including one or more processors coupled with memory configured to perform sequence optimization
one or more processors coupled with memory, configured to: identify a first sequence of write operations to configure a device, determine one or more distances between a set of the value and the address of a write operation and at least one other set of the value and the address of one or more other write operations in the first sequence of write operations, generate a second sequence of write operations based at least on the one or more distances, and cause the device to be configured using the second sequence of write operations.
Non-transitory computer readable medium storing program instructions
program instructions for causing one or more processors to: identify a first sequence of write operations to configure a device, determine one or more distances between a set of the value and the address of a write operation and at least one other set of the value and the address of one or more other write operations in the first sequence of write operations, generate a second sequence of write operations based at least on the one or more distances, and cause the device to be configured using the second sequence of write operations.
The independent claims cover identifying an initial sequence of address/value write operations, computing distances between write-operation tuples, generating a reordered and/or reduced second sequence based on those distances, and causing configuration using that second sequence across method, system, and non-transitory medium embodiments.
Stated Advantages
Reduce space taken by the configuration data.
Reduce time required to configure the device by eliminating redundant store operations.
Avoid very complicated compression schemes by using simpler encodings and hardware-supported lookups.
Significantly reduce number of SFR writes (example reduction from 3081 writes to 813 writes, nearly 75%).
Achieve compression close to gzip with simpler techniques (Huffman after other optimizations reported as within 11% of gzip at highest level).
Documented Applications
Configuring computing hardware via memory-mapped registers and sequences of register store operations.
Initializing a processor interlock (PIPE) and loading rule cache entries for security policy enforcement.
Writing initial host register tags and tag map table (TMT) entries as part of processor interlock initialization.
Storing compact configuration streams in one-time programmable (OTP) memory for device initialization.
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