Optimization of edge computing distributed neural processor for wearable devices
Inventors
Assignees
Publication Number
US-12328649-B2
Publication Date
2025-06-10
Expiration Date
2039-10-21
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Abstract
Systems and/or methods may include an edge-computing distributed neural processor to effectively reduce the data traffic and physical wiring congestion. A local and global networking architecture may reduce traffic among multi-chips in edge computing. A mixed-signal feature extraction approach with assistance of neural network distortion recovery is also described to reduce the silicon area. High precision in signal features classification with a low bit processing circuitry may be achieved by compensating with a recursive stochastic rounding routine, and provide on-chip learning to re-classify the sensor signals.
Core Innovation
The invention provides a neural processor for edge computing in distributed neural networks, specifically for wearable devices. The processor incorporates mixed-signal processing circuitry at the input stage to directly extract features from multi-channel analog signals received from various sensors. These extracted features, which include statistical values in digital format, are processed locally within the neural processor using an architecture that comprises both local and global neural network layers. On-chip memory banks store weighted ranks corresponding to each feature for the sensor inputs, enabling efficient data processing and classification within the network.
A critical problem addressed by this invention is the difficulty in designing motion classifiers for biomedical and wearable devices, which arises from the large number of sensor channels and the necessity of meeting strict communication latency requirements. Traditional solutions require transferring substantial volumes of raw sensor data to centralized processors, creating significant communication overheads and increased power consumption, thus limiting the scalability and efficiency of distributed sensor networks in wearable devices.
The proposed solution utilizes an edge-computing distributed neural network architecture where multiple neural processors, each positioned near sensor nodes, perform local classification and communicate with each other through a global network layer. The system employs a voltage-controlled oscillator-based (VCO) mixed-signal frontend to enable direct feature extraction, which significantly reduces silicon area and power consumption compared to traditional analog-to-digital conversion methods. Machine learning is performed on-chip, enhanced with reconfigurable neural network topology, recursive stochastic rounding processes for improved precision with low-bit processing, and batch training for learning and reclassification of sensor signals.
Claims Coverage
The patent contains three independent claims, each focusing on distinct yet related inventive features of the neural processor system and methods for edge computing in distributed neural networks.
Neural processor with mixed-signal feature extraction and distributed architecture
An integrated chip includes: - Mixed-signal processing circuitry at the input to extract features (statistical values in digital format) from multi-channel analog signals from sensors. - On-chip memory banks storing weighted ranks corresponding to extracted features. - A local neural network layer with neuron nodes that process features based on their weighted ranks. - A global network layer with global neuron nodes for classifying and communicating extracted features to at least one other neural processor within the distributed neural network. - The mixed-signal processing circuitry employs an on-chip, multi-channel voltage-controlled oscillator-based (VCO) frontend, where each channel includes a VCO clocked by a shared on-chip clock generator, comparators, counters, and a single-differential converter.
Distributed neural network with synchronized communication and feature-specific processing
A neural processor, in a distributed network, includes: - Mixed-signal processing circuitry at the input for multi-channel analog feature extraction. - On-chip memory banks for storing weighted ranks. - Local and global network layers formed by processing circuitry for feature processing and classification. - A distributed neural network architecture with multiple such neural processors, each local to its sensor, with one designated as a master for starting communication and providing a global clock signal for synchronization of neural processors in the network.
Neural processor with reconfigurable hidden layer topology for optimization
An integrated chip for edge computing comprising: - Mixed-signal input processing for feature extraction from multi-channel analog signals. - On-chip memory for weighted ranks storage. - Local neural network layer including an input layer and at least a first local hidden layer. - A second local hidden layer, each layer with configurable neuron nodes such that: - Each hidden layer neuron is configurable for receiving signals from prior layer neurons. - Neuron nodes in the hidden layer are configurable via crossbar connections to regroup and reconnect into different topologies, enabling tradeoffs and optimization during on-chip learning.
The inventive features collectively cover a neural processor architecture with on-chip, mixed-signal feature extraction, distributed edge-computing neural network capabilities, synchronized communication, local and global neural network layers, and reconfigurable neuron topology for application-specific optimization in wearable and distributed sensor environments.
Stated Advantages
Reduces data traffic and physical wiring congestion between sensor nodes in distributed edge computing systems.
Minimizes power consumption, with processor power usage as low as 20 uW, which is about ten-thousand times less than conventional clinically used microprocessors.
Reduces communication latency and memory requirements for processing data from multiple sensors through local edge neural processing.
Significantly decreases required silicon area for feature extraction by employing mixed-signal circuitry instead of traditional ADCs, achieving up to twenty-eight times reduction.
Optimizes bandwidth efficiency and minimizes communication bottlenecks among multi-chip edge computing networks.
Enables high-precision feature classification with low-bit processing circuitry by compensating with a recursive stochastic rounding routine.
Permits on-chip learning and reclassification of sensor signals for improved adaptability and accuracy.
Documented Applications
Wearable devices requiring high-performance, low-power computing such as cyber-gloves and prosthetic limbs, enabling stringent control of assistive devices.
Biomedical signal processing, including physiological signals like electromyography (EMG) and electrocardiography (ECG) for rehabilitation applications.
Internet of Things (IoT) devices requiring distributed sensor fusion and on-device data classification.
Human cognitive assistance, virtual reality, and gaming devices that utilize sensor networks for real-time input and motion classification.
Neural network accelerators for wearable or portable applications with stringent energy and latency requirements.
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