Method for pulse-based convolution for near-sensor processing
Inventors
Najafi, Mohammad Hassan • Faraji, S. Rasoul • Bazargan, Kiarash • Lilja, David
Assignees
University of Louisiana at Lafayette • University of Minnesota System
Publication Number
US-12299556-B2
Publication Date
2025-05-13
Expiration Date
2041-05-27
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Abstract
Disclosed herein is a low-cost, high-performance, and energy-efficient near-sensor convolution engine based on pulsed unary processing. The disclosed engine removes the necessity of using costly analog-to-digital converters. Synthesis results show that the proposed pulse-based design significantly improves the hardware cost and energy consumption compared to the conventional fixed-point binary and also to the stochastic computing-based designs.
Core Innovation
The invention discloses a low-cost, high-performance, and energy-efficient near-sensor convolution engine based on pulsed unary processing. The engine operates by converting all input data to pulse signals, which are generated using analog-to-time converters such as pulse-width modulation (PWM) signal generators. Multiplication operations are performed in the pulsed unary domain using AND gates, and the results are accumulated using an active integrator, resulting in an analog voltage output.
This design removes the need for costly analog-to-digital converters (ADCs) by processing time-encoded sensor outputs directly. The engine is structured in three main blocks: PWM signal generators for converting analog input data to PWM signals, AND gates for performing pulse-domain multiplications, and a time-to-voltage converter (integrator) that accumulates and integrates the multiplication results over time. The integrator utilizes consistent current sources and a capacitor to achieve efficient and linear accumulation of outputs.
A known limitation in the field is that conventional fixed-point binary designs, though fast and accurate, are complex, costly, and require ADCs unsuitable for near-sensor applications. Stochastic and prior pulse-based computing approaches reduce cost but suffer from high latency, increased energy consumption, or inadequate accuracy. The disclosed engine leverages deterministic pulsed unary processing to combine low hardware cost, analog-domain operation, and compatibility with sensor output, while maintaining improved accuracy and efficiency over stochastic counterparts.
Claims Coverage
There are two principal independent claims, defining the inventive features of a bipolar near-sensor convolutional engine and a method for pulse-based convolution in neural networks.
N×N bipolar near-sensor convolutional engine using pulse-based unary processing
The engine comprises: - Two or more pulse width modulation (PWM) signal generators to receive analog input signals. - Two or more AND gates configured to perform multiplications in a pulsed unary domain, with their outputs connected to a time-to-voltage converter. - The time-to-voltage converter includes an integrator with the functionality to integrate the outputs of the AND gates. - The integration process occurs in the analog domain, converting AND gate outputs to corresponding currents accumulated via a capacitor, where each input applies current based on the length of its signal’s high phase. The integrator uses identical current sources for all inputs. - Two PMOS transistors are used to implement a current source that routes current to the capacitor. In the high phase of the output signal, one PMOS transistor applies current to the capacitor; in the low phase, the other sinks current to ground.
Method for performing pulse-based convolution in a neural network
The method involves: 1. Providing an N×N bipolar near-sensor convolutional engine with two or more PWM signal generators, AND gates for pulsed unary domain multiplication, and a time-to-voltage converter. 2. Each PWM signal generator converts analog input data to PWM signals with a corresponding duty cycle. 3. The time-to-voltage converter accumulates and integrates the output signals over time, generating an analog voltage output. 4. The integrator integrates AND gate outputs in the analog domain by converting outputs to currents and integrating them in a capacitor. 5. Two PMOS transistors are used to route current sources to the capacitor: during the high phase of the output signal, one PMOS transistor sinks current into the capacitor, and in the low phase, one sinks into ground. - The method allows for the use of two inharmonic frequencies for the input pulse signals, adjustable for needed accuracy. - Positive and negative weights can be determined and fixed during neural network inference.
The claims protect a pulse-based convolutional engine and related method featuring direct analog-to-pulse conversion, multiplication and summation in the pulsed unary domain, analog domain integration via specialized PMOS circuitry, and applicability to both positive and negative weights, targeting near-sensor and neural network applications.
Stated Advantages
The design eliminates the need for costly analog-to-digital converters by processing sensor outputs directly as pulse signals.
The pulse-based convolution engine achieves significantly reduced hardware cost and energy consumption compared to conventional fixed-point binary and stochastic computing-based designs.
The area footprint is minimal due to use of an active integrator instead of costly binary adders.
The design delivers high performance with improved latency and power consumption compared to existing architectures.
Documented Applications
Near-sensor convolutional neural networks for computer vision applications.
Processing data from sensors in the analog domain in applications where time-encoded sensor outputs are provided.
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