Modular, extensible computer processing architecture
Inventors
Karageorgos, Ioannis • Sriram, Karthik • Vesely, Jan • Manohar, Rajit • Bhattacharjee, Abhishek
Assignees
Publication Number
US-12236246-B2
Publication Date
2025-02-25
Expiration Date
2040-12-08
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Abstract
One aspect of the invention provides a computer processing architecture including: a plurality of processors, each processor configured to: receive a set of data from one or more input channels or from another processor; execute at least one of a plurality of individualized processes on the data; and output the processed data according to an independent clock domain of the processor; a plurality of switches, wherein each switch connects a processor to an input channel of the one or more input channels or to another processor; and a micro-controller configured to: receive the processed data; control the plurality of switches by activating or deactivating each switch; generate a pipeline of processors from activating and deactivating the plurality of switches; and select one or more individualized processes of the plurality of individualized processes that each processor within the pipeline executes.
Core Innovation
The invention provides a modular, extensible computer processing architecture comprising a plurality of processing elements, each capable of receiving data from one or more input channels or from other processing elements, executing at least one individualized process on the data, and outputting processed data according to the element's own independent clock domain. The processing elements are interconnected by a plurality of switches, which are independently controllable to establish data pathways or “pipelines” tailored for specific tasks or processing orders.
A micro-controller oversees the system by controlling the switches, activating or deactivating them to dynamically generate and reconfigure pipelines of processing elements as needed. This micro-controller also selects which individualized process each processing element should execute within a pipeline and receives the processed data for further operations. Critically, the architecture operates within stringent power budgets and supports asynchronous communication between processing elements to maximize efficiency and minimize resource usage.
The problem addressed by the invention is the lack of a general-purpose, low-power, extensible platform suitable for demanding applications such as implantable brain-computer interfaces (BCIs), where modularity, scalability, and the ability to integrate new processing capabilities are essential. Existing microelectronic systems for BCIs face challenges in meeting strict requirements for low power, real-time performance, modularity, extensibility, and broad applicability across different diseases, brain regions, and computational needs. The invention solves these challenges by providing a configurable architecture that can be adapted for various processing tasks while maintaining safe operation under strict power and performance constraints.
Claims Coverage
There is one independent claim, which defines multiple inventive features relating to the composition and modular configuration of a computer processing architecture.
Configurable pipeline of processing elements with independent clock domains
The architecture includes a plurality of processing elements, each designed to: - Receive data from one or more input channels or from other processing elements. - Execute at least one individualized process distinct from those of other processing elements. - Output processed data using its own independent clock domain, which can differ from others in the system. This supports asynchronous operation and enables element-specific processing and power management.
Switch-controlled dynamic interconnection of processing elements
A plurality of switches connect processing elements to input channels or to other processing elements. Each switch can be controlled (activated or deactivated) independently, allowing for the creation and reconfiguration of data pipelines between the elements, supporting flexible processing arrangements without hardware changes.
Micro-controller management of pipelines and individualized processes
A micro-controller is configured to: - Control the activation state of each switch, thereby generating pipelines of processing elements. - Select which individualized processes (from a plurality of available options) each processing element within a pipeline will execute. - Receive the processed data from the processing elements for further use or transmission. This enables dynamic selection and management of processing tasks based on operational requirements.
Restricting architecture to application-specific processing elements and power constraints
The processing elements are characterized by being distinct from general purpose CPUs, GPUs, or SIMD processing units. The pipelines established via the architecture are required to operate within a 15 mW power budget, making the system suitable for power-constrained applications.
The inventive features encompass a modular and extensible processing architecture wherein application-specific processing elements—interconnected and controlled by programmable switches and a micro-controller—provide asynchronous, reconfigurable pipelines for individualized processing tasks under strict power constraints, distinct from traditional general-purpose architectures.
Stated Advantages
Enables modularity and extensibility, allowing new processing elements to be added or removed to adapt to evolving requirements and capabilities.
Operates within stringent power budgets, ensuring safe use in power- and heat-constrained environments such as implantable brain-computer interfaces.
Supports real-time, closed-loop processing essential for applications like seizure mitigation and movement intent detection.
Provides a general-purpose architecture for a wide range of processing tasks and medical applications, overcoming the fragmentation of specialized, single-purpose designs.
Improves system efficiency with asynchronous communication and individualized, parameterizable processes for each processing element.
Reduces device resource usage and increases processing efficiency through configurable pipelines and power-saving microarchitectural optimizations.
Documented Applications
Implantable brain-computer interfaces (BCIs) for neurological disease treatment and brain signal processing.
Seizure onset prediction and mitigation in epilepsy patients through closed-loop neural monitoring and stimulation.
Movement intent detection for treatment of movement disorders like Parkinson's disease and control of prostheses for paralyzed individuals.
Compression of neuronal data to reduce radio transmission bandwidth and limit RF power deposition in medical implants.
Neural activity spike detection for spike-sorting and bandwidth reduction in BCI data transmission.
Data encryption for secure transmission of neural and medical data in compliance with standards such as HIPAA and NIST.
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