Systems and methods for identifying counterfeit memory
Inventors
Ray, Biswajit • Milenkovic, Aleksandar
Assignees
Board Of Trustees For University Of Alabama For And On Behalf Of University Of Alabama In Huntsville • University of Alabama in Huntsville
Publication Number
US-12159053-B1
Publication Date
2024-12-03
Expiration Date
2042-05-24
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Abstract
A memory authentication system initiates various memory operations on a memory chip and then assesses the performance of the memory chip in performing such operations in an attempt to identify a signature in the chip's performance that can be used to identify the chip's source. As an example, a partial erase operation may be performed on programmed memory cells in order to drain some charge from the cells but allowing some charge to remain in the cells. Due to process variations during manufacturing, charge should drain from the cells at different rates such that some of the cells may flip to an erase state while other cells remain in a program state. The pattern of bit flips defines a unique signature that may be used to identify the chip's manufacturing source (e.g., the foundry at which the chip was manufactured).
Core Innovation
The invention relates to systems and methods for authenticating memory, particularly by exploiting systematic process variations in memory chip manufacturing to generate unique signatures for each chip. The system programs memory cells of a block, performs a partial erase operation to partially drain charge from the cells, and then reads the resultant states of the memory cells. The resulting pattern of bit flips, due to manufacturing process variations, serves as a unique signature that can be matched against known signatures to identify the chip's manufacturing source.
The problem addressed by this invention is the proliferation of counterfeit memory chips in the market, especially in nonvolatile memories like NAND flash, which can result in unreliable products with shorter lifespans and potential failures in critical applications. Current methods for detecting counterfeit memory chips, such as physical inspections, parametric functionality tests, use of Electronic Chip Identifiers (ECIDs), or Physical Unclonable Functions (PUFs), are costly, require expert knowledge, or are not practical for widespread use.
This invention proposes an efficient and cost-effective methodology for authenticating memory chips without the need for experts. By controlling the memory controller to execute specific partial erase operations, observing the state of memory cells, and comparing the observed signature pattern to predefined data representative of authentic chips from various manufacturing sources, the system can accurately identify authentic versus counterfeit memory chips.
Claims Coverage
The patent includes three independent claims, covering inventive features related to electronic devices and methods for memory authentication.
Executing partial erase and analyzing page-wise parameters
An electronic device comprising memory with blocks of memory cells and at least one processor programmed to: - Control a memory controller to perform a partial erase operation on the block of memory cells, resulting in a partially-erased state. - Read the block of memory cells in the partially-erased state. - For each page, determine a parameter indicative of the number of memory cells in an erase state. - Determine a pattern of this parameter across pages. - Compare this pattern to predefined signature data indicative of manufacturing sources. - Identify the memory's manufacturing source based on this comparison.
Performing memory operation and signature-based source identification
An electronic device comprising memory with blocks of memory cells and at least one processor programmed to: - Control a memory controller to perform a memory operation (not limited to partial erase) on the block of memory cells. - Read the block after the operation. - For each page, assess performance of the memory operation by determining a parameter indicative of a number of memory cells in a particular state. - Determine a pattern of this parameter across pages. - Compare this pattern to predefined signature data for manufacturing sources. - Identify the source based on the comparison.
Method for authenticating memory by partial program operation and pattern analysis
A method comprising: 1. Performing a partial program operation (partial erase) on a block of memory cells with multiple pages. 2. Performing at least one read operation on the block in its partially-erased state. 3. For each page, determining a parameter indicative of a number of memory cells in an erase state. 4. Determining a pattern of the parameters across the pages. 5. Comparing the pattern to predefined data of known signatures for manufacturing sources. 6. Identifying the manufacturing source of the memory based on the comparison.
The claims broadly cover electronic devices and methods that perform partial erase or other memory operations, analyze the resultant changes in memory cell states, and compare observed patterns to predefined signatures to identify the manufacturing source of a memory chip.
Stated Advantages
Provides an efficient, easy-to-use, and cost-effective methodology for authenticating memory chips without requiring expert involvement.
Facilitates widespread adoption and use by eliminating the need for high-cost, complex, or expert-dependent authentication techniques.
Effectively distinguishes genuine memory chips from counterfeits based on intrinsic physical characteristics resulting from manufacturing process variations.
Documented Applications
Authenticating NAND flash memory chips to eliminate counterfeits in electronics supply chains.
Ensuring reliable memory components in mission-critical systems, medical systems, and consumer-level products requiring robust lifecycles.
Deployment in devices including smartphones, mobile devices, tablets, personal computers, game consoles, memory cards, USB flash drives, and solid-state drives.
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