Field effect transistor, device including the transistor, and methods of forming and using same
Inventors
Assignees
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Publication Number
US-12007389-B2
Publication Date
2024-06-11
Expiration Date
Abstract
The present disclosure provides an improved field effect transistor and device that can be used to sense and characterize a variety of materials. The field effect transistor and/or device including the transistor may be used for a variety of applications, including genome sequencing, protein sequencing, biomolecular sequencing, and detection of ions, molecules, chemicals, biomolecules, metal atoms, polymers, nanoparticles and the like.
Core Innovation
The invention provides a sensor device that combines a field effect transistor architecture with a solid-state nanopore. A substrate having a first surface and a second surface opposite the first surface includes an etch region, and an insulating region is formed within the substrate and proximate the etch region. A semiconductor layer overlies the insulating region and supports a source region, a drain region, and a channel region formed from separate portions of the semiconductor layer.
The device includes a nanopore formed within the etch region, and the channel is formed as a bi-feature having an opening of less than 1000 nm. The architecture places the insulating region proximate the nanopore region so that the channel region is associated with the nanopore-containing etch region, enabling FET-based readout using amplified response to nanopore-related electric field effects as presented in the disclosed narrative.
A method is also provided for forming the sensor device by etching a substrate to form an etch region open to both surfaces to thereby form a nanopore, forming an insulating region proximate the etch region, forming a thin film overlying the insulating region, and forming a source region on one side of the nanopore and a drain region on the other side of the nanopore. The channel region is formed between the source region and the drain region, and the disclosed method includes forming a thin film and structuring device regions so the nanopore and channel regions are integrated.
Claims Coverage
The independent claims are directed to a semiconductor sensor device architecture and a method of forming the sensor device. Across the two independent claims, the main inventive features include a nanopore formed in an etch region integrated with a buried insulating region and a semiconductor channel configured as a bi-feature, as well as a fabrication sequence that etches a nanopore, forms an insulating region and a thin film, and defines source and drain regions separated by a channel region.
Nanopore-integrated substrate with proximate insulating region and bi-feature channel opening
A device comprising a substrate with an etch region; an insulating region formed within the substrate proximate the etch region; a semiconductor layer overlying the insulating region; a source region, drain region, and a channel formed using respective portions of the semiconductor layer; a nanopore formed within the etch region; wherein the channel is formed as a bi-feature having an opening of less than 1000 nm.
Method forming a nanopore sensor device with insulating region, thin film, and source/drain defining channel region
A method of forming a sensor device by providing a substrate; etching a portion of the substrate to form an etch region open to first and second surfaces and thereby form a nanopore; forming an insulating region proximate the etch region; forming a thin film overlying the insulating region; forming a source region using the thin film on one side of the nanopore; and forming a drain region using the thin film on a second side of the nanopore, wherein a channel region is formed between the source region and the drain region.
Overall, the independent claims cover an integrated nanopore and FET-like semiconductor structure where a buried insulating region is proximate the nanopore and the channel geometry is specified as a bi-feature with an opening under 1000 nm, and a corresponding fabrication method that etches a nanopore, forms an insulating region and thin film, and then forms source and drain regions to create the channel between them.
Stated Advantages
Not explicitly described in patent.
Documented Applications
Not explicitly described in patent.
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