Nanopore sensor, structure and device including the sensor, and methods of forming and using same
Inventors
Assignees
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Publication Number
US-11977069-B2
Publication Date
2024-05-07
Expiration Date
Abstract
The present disclosure provides an improved device that can be used to sense and characterize a variety of materials. The device may be used for a variety of applications, including genome sequencing, protein sequencing, biomolecular sequencing, and detection of ions, molecules, chemicals, biomolecules, metal atoms, polymers, nanoparticles and the like.
Core Innovation
The problem addressed is the need for ultrasensitive and ultrafast characterization/sequencing of biomolecules and the detection of ions/molecules, while improving upon limitations associated with ion-current blockade and prior nanopore platforms. The disclosure presents an improved nanopore sensor/device referred to as a Field Effect Nanopore Transistor (FENT).
In the FENT concept, sensing is performed using a fully-depleted field-effect transistor inversion/accumulation current that is modulated by electrostatic interactions at a nanopore aperture. The approach includes electrostatic double edge-field and fully-depleted amplification to obtain high signal-to-noise at operation in the MHz-GHz range.
The disclosure also describes multiple device architecture options in which a nanopore is integrated with a field-effect transistor structure, including variations of substrate types, channel and surrounding nanopore geometry, gate oxide and gate metal, encapsulation, and additional functional layers and thin films. It further describes sensor arrays in which multiple devices surround one or more nanopores to support redundant combinatorial detection arrays (RCDA), as part of the characterization/sequencing platform.
Claims Coverage
One independent claim is provided (clm-00001). It covers a method of forming a semiconductor device with source/drain regions, a channel region, a moat region with a deposited/grown gate dielectric material, and one or more nanopores within the semiconductor layer, using a spacer formed about a structure to enable moat formation; dependent claims refine nanopore sizing, nanopore formation control/termination, and gate geometry.
Semiconductor device formation with source, drain, channel, structure, spacer, and moat
A method of forming a device comprising providing a substrate with a semiconductor layer including a source region proximate a first surface and a drain region proximate a second surface, etching a portion of the substrate to form a substrate etch region, forming a channel within a third portion of the semiconductor layer, forming a structure on the semiconductor layer, forming a spacer about the structure, using the spacer to form a moat region about the spacer within the semiconductor layer, and forming one or more nanopores within the semiconductor layer.
Gate dielectric material in the moat region
Depositing or growing a gate dielectric material within the moat region as part of the device formation in which one or more nanopores are formed within the semiconductor layer.
Nanopore opening size range
Forming one or more nanopores within the semiconductor layer such that the nanopores comprise an opening between about 1 nm and about 100 nm.
Nanopore formation control and termination mechanisms
Forming the one or more nanopores using a wet etchant and controlling nanopore formation by one or more mechanisms including electric current feedback monitoring, capacitance measurement monitoring, chemical-stop etching, and/or material-aggregate formation that physically stops further nanopore formation.
Etch stop before nanopores form using specific electrical measurements
During formation of the one or more nanopores, stopping the etching before the nanopores form based on measurements of one or more of electrical current, capacitive, and conductance measurements.
C-shaped or V-shaped gate region geometry
Configuring the gate region to be C-shaped or V-shaped.
Additional layers comprising specified material classes
Including additional layers that comprise organic molecules or biomolecules, semiconducting materials, metals, semi metals, insulators, dielectric materials, or meta-materials.
The claim set covers forming an FET-compatible nanopore semiconductor structure with a spacer-enabled moat and a gate dielectric within the moat, followed by formation of one or more nanopores. The dependent claims further specify nanopore opening size, multiple nanopore formation control/termination approaches using wet etch plus electrical, chemical, and material-aggregate stop criteria, and refinements including C-shaped/V-shaped gate geometry and allowed material classes for additional layers.
Stated Advantages
High signal-to-noise at MHz-GHz operation.
Ultrasensitive and ultrafast characterization/sequencing of biomolecules and detection of ions/molecules.
Documented Applications
Ultrasensitive and ultrafast characterization/sequencing of biomolecules including DNA/RNA and proteins.
Detection of ions/molecules.
Protein sequencing and characterization of protein post-translational modifications (PTMs) and protein mutations.
Genome sequencing and genome diagnostics using epigenetic DNA/histone marks including DNA methylation (5 mC), hydroxymethylation (5 hmC), formylation (5 fC), and carboxylation (5 caC).
Disease diagnosis including cancer and Alzheimer’s/neurodegeneration, including Tau, amyloid, and alpha-synuclein.
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