Integrity verification system for testing high channel count neuromonitoring recording equipment

Inventors

Rhodes, Ethan • Villarreal, Richard A. • Cadwell, John A. • Rehfeldt, Rose

Assignees

Cadwell Laboratories Inc

Abstract

Methods of performing diagnostic tests on electroencephalography (EEG) recording devices comprising at least one stimulator coupled with a plurality of EEG electrode recording channels and corresponding recording channel connectors are performed by a test fixture comprising a plurality of resistors coupled with one or more of the EEG electrode recording channels and corresponding recording channel connectors. The methods include performing an impedance test for determining if each EEG recording channel of the EEG recording device has a predefined impedance, performing a channel uniqueness test for each EEG recording channel, performing a test for verifying the state of a switch of the stimulator of the EEG recording device, and performing a test for verifying connector IDs of the recording channel connectors connecting the EEG electrodes to respective EEG recording channels.

Core Innovation

The invention describes an integrity verification system (IVS) for an electroencephalography (EEG) recording device having a plurality of EEG electrode recording channels and at least one stimulator. The IVS uses a hardware test fixture together with internal and/or external stimulator test circuitry and software diagnostics to perform diagnostic testing for large channel count neuromonitoring systems. The system is configured to verify channel integrity, impedance, and functionality for each EEG electrode recording channel.

The IVS performs an impedance test to determine whether each EEG recording channel has a predefined impedance, including comparing measured impedance values to expected values using a predetermined margin of error. The IVS further performs a channel uniqueness/lead-off and electrode-contact viability verification by opening and connecting channel switches and checking connected/disconnected status for each channel. This verification is intended to determine whether electrode-contact viability is present for the channel.

The IVS also performs stimulator switch-matrix integrity tests for high-side and low-side stimulator switches. The test circuitry uses a constant-voltage test stimulator, and optionally a constant-current pulse, to generate an expected stimulus and to obtain expected voltage/ground/fractional readings for evaluation. In addition, the IVS verifies connector identification circuitry by detecting connector IDs using sequentially incrementing serial-numbered ID groups, including reverse polarity connector-ID simulation, and compares the detection results to expected connector ID behavior.

Claims Coverage

The partial content identifies one independent claim covering three core diagnostic checks for each EEG recording channel on an EEG recording device that includes a stimulator with multiple recording channels.

Across the independent claim and its refinements, the diagnostic coverage is organized around determining whether each channel impedance matches a predefined impedance, verifying channel uniqueness via connected status using a hardware testing device, and verifying functionality, including connector identification circuitry behavior and switch-matrix integrity testing for stimulator high-side and low-side switches.

Stated Advantages

Documented Applications