Ic with graphene fet sensor array patterned in layers above circuitry formed in a silicon based cmos wafer
Inventors
Goldsmith, Brett R. • Lerner, Mitchell • Hoffman, Paul
Assignees
Publication Number
US-11782057-B2
Publication Date
2023-10-10
Expiration Date
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Abstract
An integrated circuit (IC) chip includes ROIC circuitry in a CMOS wafer with a top dielectric layer and at least one graphene field effect transistor (gFET) sensor array added above the CMOS wafer. The IC chip includes access transistors controlled by the ROIC circuitry and further includes sensing circuitry which includes the at least one gFET sensor array and a passivation opening that allows direct contact of a sample liquid with the graphene channels of the gFETs in the at least one gFET sensor array, such that a liquid gate is formed above the graphene channel upon receipt of the sample liquid. In some examples, the IC chip includes a process, memory controller, and memory. A system and a method have similar structures and perform the functions of the apparatus.
Core Innovation
The invention provides an integrated circuit chip in which read out integrated circuit (ROIC) circuitry is formed in a silicon based CMOS wafer that includes a top dielectric layer acting as a first insulating layer, and at least one graphene field effect transistor (gFET) sensor array is added above the CMOS wafer. Access transistors formed in the CMOS wafer are controlled by the ROIC circuitry to access corresponding sensing transistors of the gFET sensor array, and sensing circuitry comprising the gFETs is added above the wafer so that the gFETs serve as the sensing transistors. The gFETs include a passivation opening that allows direct contact of a sample liquid with the graphene channels such that a liquid gate is formed above the graphene channel upon receipt of the sample liquid.
Each sensing transistor is described as including a graphene channel patterned in a two‑dimensional layer of graphene transferred to a first insulating layer at the top surface of the CMOS wafer, and gFET source and drain patterned in a conductive layer with the graphene channel extending between them. The IC chip can include one or more reference electrodes formed in a top metal layer adjacent to the gFET sensors so as to contact the sample liquid, and two or more reference electrodes can be configured so that at least one applies a liquid gate voltage and at least one measures a liquid gate voltage (VGS).
The chip-level structure is presented with on‑chip electronics: the ROIC circuitry can include address decoder circuitry to select individual gFET sensing transistors, and the CMOS wafer can include a processor, memory controller, and memory disposed below the ROIC. The processor is described to process and analyze signals from selected gFETs to generate current versus gate voltage (I‑Vg) curves and to determine I‑Vg curve parameters (e.g., ION, transconductance gm, Dirac voltage) to determine characteristics of the sample liquid such as presence of analytes, changes in analyte concentration, biologic activity, and analyte identity.
Claims Coverage
Independent claims identified: 1, 19, and 20. Main inventive features concern (i) an IC chip integrating ROIC and access transistors in a CMOS wafer with gFET sensor arrays added above, (ii) a manufacturing method to form such an IC, and (iii) a system including the IC and fluidics for delivering sample liquid.
ROIC circuitry with top dielectric insulating layer
read out integrated circuit (“ROIC”) circuitry formed in a silicon based CMOS wafer that includes a top layer of dielectric material that acts as a first insulating layer between the CMOS wafer and at least one graphene field effect transistor (“gFET”) sensor array added above the CMOS wafer.
Access transistors formed in the CMOS wafer
access transistors controlled by circuits of the ROIC circuitry for accessing corresponding sensing transistors of the at least one gFET sensor array, the access transistors formed in the CMOS wafer and individually comprising: a conductive gate associated with a gate dielectric that acts as an insulating barrier separating the gate from a semiconductor channel, the semiconductor channel being formed by charge carriers in a silicon based semiconductor material connecting a source region and a drain region when a threshold gate voltage is applied; a conductive source contact coupled to a source region at a first end of the semiconductor channel; a conductive drain contact coupled to a drain region at a second end of the semiconductor channel.
gFET sensing circuitry added above the CMOS wafer
sensing circuitry added to the CMOS wafer and comprising the graphene field effect transistors (“gFETs”) of at least one gFET sensor array, the gFETs serving as the sensing transistors and individually comprising: a graphene channel patterned in a two-dimensional (2D) layer of graphene transferred from a growth substrate to a first insulating layer at a top surface of the CMOS wafer; a gFET drain patterned in a conductive layer; and a gFET source patterned in the conductive layer, where the graphene channel extends between the gFET source and the gFET drain.
Passivation opening forming a liquid gate
a second insulating layer that acts as a passivation layer added above the gFET sources and the gFET drains of the sensor array, the second insulating layer patterned to form a passivation opening that allows direct contact of a sample liquid with the graphene channel, such that a liquid gate is formed above the graphene channel upon receipt of the sample liquid.
Reference electrodes contacting sample liquid
one or more reference electrodes formed in a top metal layer of the IC chip adjacent to one or more of the gFET sensors of the at least one gFET sensor array so as to contact the sample liquid, and two or more reference electrodes where at least one is configured to apply a liquid gate voltage to the liquid and at least one is configured to measure a liquid gate voltage (VGS) of the liquid.
Method of forming ROIC, access transistors, and gFET sensing circuitry
forming read out integrated circuit (“ROIC”) circuitry in a silicon based CMOS wafer that includes a dielectric material on top; forming in the CMOS wafer a plurality of access transistors controlled by the ROIC circuitry for accessing corresponding sensing transistors of one or more gFET sensor arrays; adding sensing circuitry above the CMOS wafer comprising graphene field effect transistors (gFETs) of at least one gFET sensor array with gFET drains and gFET sources patterned in or on the dielectric material at the top of the CMOS wafer and a graphene channel patterned in a two-dimensional layer of graphene transferred from a growth substrate and aligned to efficiently contact the gFET drain and gFET sources.
System including IC chip and fluidics
a system comprising an integrated circuit (“IC”) chip as recited above and a fluidics component that includes a fluid source comprising a reservoir with one or more fluids therein and configured for delivering the one or more fluids to contact selected gFETs of the at least one gFET sensor array.
The independent claims cover an integrated CMOS IC with ROIC and access transistors below an added gFET sensor array whose graphene channels are exposed via passivation openings to form a liquid gate; a corresponding manufacturing method to form ROIC, access transistors, and above‑wafer gFET sensing circuitry including transferred graphene channels; and a system combining the IC with fluidics to deliver sample liquid to the gFET array.
Stated Advantages
Increased sensor sensitivity and improved signal‑to‑noise characteristics relative to conventional transistor‑based sensors, achieved by using 1D/2D nanomaterial channels (e.g., graphene) and optimized channel transconductance.
Scalability and dense sensor arrays by integrating gFET sensor arrays directly above CMOS ROIC circuitry, enabling large numbers of sensors on a single chip.
On‑chip processing and readout capability via ROIC circuitry and an on‑chip processor to generate and analyze I‑Vg (ID‑VGS) curves and determine analyte presence, concentration changes, biologic activity, or analyte identity.
Ability to form a solution (liquid) gate by a passivation opening that allows direct contact of sample liquid with the graphene channel, and to use reference electrodes to apply and measure liquid gate voltages.
Support for high‑density, high‑throughput biochemical sensing (including sequencing workflows) by combining gFET arrays with fluidics and on‑chip memory/control.
Documented Applications
Analysis of biological or chemical materials, including detection of analytes and monitoring of biologic activity.
Nucleic acid hybridization and detection, including DNA and RNA detection.
Next Generation Sequencing (NGS) applications, including DNA/RNA sequencing by sensing reactions proximate to gFET channels.
Genetic diagnostics, genome identification, species identification, nucleic acid capture, and genotyping.
Whole genome analysis, exome analysis, panel analysis, and microarray analysis.
Microbial and microbiome analysis.
Clinical analyses including cancer analysis, non‑invasive prenatal testing (NIPT), cfDNA, and blood/plasma/serum analysis.
Biosensing modalities including antibody–antigen detection and cell monitoring.
Enzyme FET (EnFET) and other chemically‑sensitive FET implementations for chemical and biological analysis.
Integration in systems combining IC chips (processor/memory/ROIC) with fluidics for automated sample delivery and sensor readout.
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