Custom mass multiplication circuits

Inventors

Mathews, Mark Ashley

Assignees

Gigantor Technologies Inc

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Publication Number

US-11748061-B2

Patent

Publication Date

2023-09-05

Expiration Date


Abstract

A mass multiplier implemented as an integrated circuit has a port receiving a stream of discrete values and circuitry multiplying each value as received by a plurality of weight values simultaneously. An output channel provides products of the mass multiplier as produced. The mass multiplier is applied to neural network nodes.

Core Innovation

The invention describes a mass multiplier integrated circuit for convoluted neural network (CNN) computation that operates on a stream of discrete data values. Input values are received continuously column by column and line by line from a matrix of data values, and output values are produced in a continuous stream. The circuitry simultaneously multiplies each input data value by a plurality of weight values of a specific aperture function to create a set of products.

The mass multiplier includes second hardware circuitry that performs a subfunction of the specific aperture function for each data value received. This second circuitry uses individual ones of the set of products to produce partial output values for the aperture function. Third hardware circuitry retains the partial output values and provides the partial output values back to the first hardware circuitry as needed to produce complete output values.

The document further specifies embodiments in which input values are unsigned binary fixed width and the plurality of weight values include unsigned binary fixed width weights with at least two bits. The products are constructed via summations of bit-shifted duplicates, with optional subtraction-based optimization, omission of unused shifted terms or products, and pipeline implementations including combinational logic as well as single-stage and multi-stage pipelining constrained by limits on addends per stage.

Claims Coverage

The independent claim defines a mass multiplier operating as part of an integrated circuit implementing a CNN, with a continuous-stream architecture. The inventive features center on simultaneous multiplication by aperture-function weights, aperture-function subfunction computation from products, and feedback retention to produce complete output values in a continuous stream.

Continuous-stream mass multiplier for CNN on an integrated circuit

A mass multiplier operating as part of an integrated circuit implementing a convoluted neural network (CNN), including a port receiving a stream of discrete data values column by column and line by line from a matrix of data values and producing output values in a continuous stream.

Simultaneous multiplication by aperture-function weights

First hardware circuitry multiplying each data value as received by a plurality of weight values of a specific aperture function simultaneously, creating a set of products.

Aperture-function subfunction from individual products

Second hardware circuitry performing a subfunction of the specific aperture function for each data value as received, using individual ones of the set of products, producing partial output values for the aperture function.

Retaining partial outputs and feedback to produce complete outputs

Third hardware circuitry retaining the partial output values and providing the partial output values back to the first hardware circuitry as needed to produce complete output values.

Bit-shifted-duplicate product construction

Input values received as unsigned binary fixed width and unsigned binary fixed width weights of at least two bits, with each product formed as a sum of bit-shifted duplicates of the input values.

Subtraction optimization via increased shifted-duplicate set

An increased set of shifted duplicates enabling subtraction operations to reduce or otherwise optimize the circuit.

Omission of unused shifted-duplicate outputs

Allowing omission of unused outputs from a set of shifted duplicates.

Single-stage pipeline timing for products

Products generated by a single-stage pipeline using one or more clock cycles.

Multi-stage pipeline constrained to two addends per stage

Products generated by a multi-stage pipeline combining no more than two addends per stage.

Overall claim coverage defines a continuous-stream integrated-circuit mass multiplier for CNN computation, including simultaneous aperture-function-weight multiplication, partial aperture subfunction computation from products, and retention and feedback of partial outputs to form complete continuous outputs. Dependent claim refinements further constrain digital representations and specify product construction using bit-shifted duplicates, optional subtraction optimization, omission of unused shifted outputs, and specific pipeline structures including single-stage and multi-stage pipelining with addend limits.

Stated Advantages

Not explicitly described in patent.

Documented Applications

Not explicitly described in patent.

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