Unit for a bus system, master-slave bus system with a plurality of units, and method for addressing units of a bus system
Inventors
Fessel, Andreas • Humm, Markus
Assignees
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Publication Number
US-11714768-B2
Publication Date
2023-08-01
Expiration Date
Abstract
The disclosure relates to a unit for a bus system, a master/slave bus system with such units, and a method for assigning individual unit addresses for units of a bus system, wherein through the use of an enable signal, which is relayed from unit to unit, only one unit is respectively in an allocation mode in which the unit that is respectively in the allocation mode is allocated an individual unit address so that the units of the bus system can each be allocated with the unique individual address one after the other in the sequence of their cabling.
Core Innovation
The invention relates to a unit for a bus system, including a bus interface, a control input for receiving an input signal, and a control output for sending an output signal. The control input is connected to an input circuit for processing the input signal, and the control output is connected to an output circuit for generating the output signal. The unit includes an address memory configured to store a collective broadcast address and an individual unit address.
In the unit, the output circuit generates the signal present at the control output from a supply voltage of the unit or from an external voltage. The control output can be implemented so that the generated signal is present as a digital output signal, an analog output signal, or as an open collector output with a digital signal. The address memory can further store an individually assigned address and, in some configurations, a collective allocation address.
The invention also provides an addressing method for a plurality of units connected via at least one bus line to a master to form a bus system. Respective pairs of units are connected in series by control lines that connect a control output of a first unit to a control input of a second unit, such that all units are connected in series from an initial unit to a last unit. The method switches the units from operating mode into addressing mode, in which inhibiting signals are generated and propagated unit-to-unit so that allocation is enabled sequentially.
After switching into addressing mode, the first unit in the series is switched into an allocation mode by transmission of an enable signal to the control input of the initial unit. An address is allocated to the unit in allocation mode by transmission via the bus line, and the address is stored as an individual unit address in the address memory. After address storage, the unit is switched into a wait mode and generates and forwards an enable signal to the next unit in series, so that repetition allocates addresses until all units are in wait mode, after which the units are switched back into operating mode.
Claims Coverage
The document includes two independent claims (a unit and a method). The independent claim set defines core inventive features covering (i) the bus-system unit with input/output circuits and an address memory, and (ii) a series-connected, stepwise addressing/allocation/wait method using inhibiting signals and enable signaling propagated unit-to-unit via control lines.
Bus-system unit with collective broadcast address and individual unit address
A unit for a bus system having a bus interface; a control input for receiving an input signal and a control output for sending an output signal; wherein the control input is connected to an input circuit for processing the input signal and the control output is connected to an output circuit for generating the output signal; an address memory embodied to store a collective broadcast address and an individual unit address; and wherein the output circuit is embodied to generate the signal that is present at the control output from a supply voltage of the unit or from an external voltage.
Series-connected control-line topology with address allocation via bus line and enable propagation
A method for addressing a plurality of units connected via at least one bus line to a master forming a bus system, where each unit has a bus interface, a control input, and a control output with an input circuit and an output circuit, and each unit has an address memory storing a collective broadcast address and an individual unit address; respective pairs of units are connected in series by a control line from a control output of a first unit to a control input of a second unit so that all units are connected in series from an initial unit to a last unit; and the method includes switching from operating mode into an addressing mode generating inhibiting signals propagated as output signals at the control output to a next unit, switching the first unit into an allocation mode by transmission of an enable signal, allocating an address to a unit in allocation mode by transmission via the bus line and storing it as an individual unit address, switching the unit into a wait mode and generating an enable signal output to the control input of the next unit, repeating for each unit until all units are in wait mode, and switching the plurality of units from wait mode into operating mode.
Across the independent claims, the inventive coverage centers on a bus-system unit with an address memory storing a collective broadcast address and an individual unit address, together with a method that uses series-connected control lines, inhibiting signals in addressing mode, and enable signal propagation so that address allocation occurs sequentially through units and units return to operating mode after allocation.
Stated Advantages
Sequentially enabling only one slave at a time to enter an allocation mode so that the individually assigned address can be stored.
A completion condition can be detected via a reply line from the last unit or via the master tracking allocations.
Documented Applications
Addressing a plurality of units connected via bus line to a master in a master/slave bus system using addressing mode, allocation mode, and wait mode.
Relaying an enable signal unit-to-unit via control lines so that allocation is performed stepwise across series-connected units.
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