Work load scheduling for multi core systems with under-provisioned power delivery
Inventors
Savidis, Ioannis • Pathak, Divya • Homayoun, Houman
Assignees
Drexel University • George Mason University
Publication Number
US-11435802-B2
Publication Date
2022-09-06
Expiration Date
2038-05-01
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Abstract
A real-time workload scheduling heuristic assigns tasks to the cores such that the total load current consumption of the cores is always less than the total current capability of the under-provisioned on-chip voltage regulators. In addition, the energy-efficient scheduling of the tasks on to the cores ensures that the reconfiguration of the power delivery network is minimized. The heuristic includes DVFS management based on the unique constraints of the under provisioned voltage regulators.
Core Innovation
The invention describes a real-time workload scheduling heuristic for multi-core systems where each core is powered by under-provisioned on-chip voltage regulators (OCVRs). The task scheduler assigns workloads to the cores such that the total load current consumption is always less than the total current capability of the under-provisioned OCVRs. The scheduling is energy-efficient and minimizes the need for reconfiguration of the power delivery network. This is achieved through a heuristic approach that manages Dynamic Voltage and Frequency Scaling (DVFS) while considering the unique constraints imposed by the under-provisioned nature of the on-chip voltage regulators.
The problem addressed by the invention is the traditional over-provisioning of on-chip voltage regulators, which leads to inefficiencies in area and energy consumption in multi-core processor systems. Existing workload schedulers and power delivery configurations often ignore the power lost in the DC-DC converters and fail to account for variations in power conversion efficiency due to DVFS. This results in suboptimal workload mappings and unnecessary energy losses, particularly because most workloads do not frequently utilize the peak current capabilities for which power delivery systems are typically designed.
To solve this, the invention introduces a system where the OCVRs are provisioned for the average, rather than the peak, current requirements of the cores. The architecture leverages a configurable High-Speed Switching (HSS) fabric and a power management unit (PMU) to dynamically combine outputs from multiple OCVRs when demand exceeds the rating of a single OCVR. The workload scheduler assigns, partitions, and schedules tasks using acceptance tests, a Marginal Power Heuristic (M-PWR), and a DVFS procedure that reduces core voltages and frequencies while adhering to power constraints. This cross-layer optimization results in improved energy efficiency and reduces unnecessary reconfiguration of the power delivery network.
Claims Coverage
The independent claims define three main inventive features describing the system architecture, the workload scheduling method, and the dynamic power delivery mechanism.
Multi-core system with under-provisioned on-chip voltage regulators and reconfigurable power delivery
The system includes: - Multiple on-chip voltage regulators (OCVRs) with peak current output set to match the average current requirements of the multiple cores, not the peak. - Multiple cores interconnected via a high-speed switching (HSS) fabric, controlled by a power management unit (PMU), which enables dynamic current sharing among cores. - A task scheduler that distributes workloads such that the total load current of active cores is always less than the cumulative current capability of the under-provisioned OCVRs. - The PMU can reconfigure the switching fabric to combine outputs of multiple OCVRs when a workload requires more current than a single OCVR can deliver, ensuring reliability under dynamic current loads.
Task scheduling method to maintain power constraints with under-provisioned voltage regulators
- The task scheduler utilizes acceptance tests for each incoming task and only assigns tasks that do not violate power constraints imposed by the under-provisioned power delivery system. - The scheduler operates in real time, distributing and balancing workloads across the cores, ensuring system power draw remains within safe operational constraints defined by the collective capacity of all OCVRs, even when these are only provisioned for average current requirements.
Real-time load balancing by dynamic combining of voltage regulator outputs
- Real-time load-balancing is accomplished by reconfiguring switches between multiple OCVRs and multiple cores. - When any core's demand exceeds the peak current supported by its attached OCVR, the PMU dynamically combines outputs from multiple OCVRs using the HSS fabric, matching the voltage levels if necessary. - Currents sensed from all cores are monitored, and if any core or cluster approaches or exceeds the average current threshold, additional OCVRs provide current to prevent system failure or stalling.
These inventive features collectively enable a multi-core system that operates energy-efficiently with under-provisioned power delivery, maintains reliable task scheduling under power constraints, and dynamically redistributes power resources at runtime to match workload demands.
Stated Advantages
Increased energy efficiency in multi-core systems by provisioning on-chip voltage regulators for average, not peak, current demand, resulting in up to 44% reduction in energy consumption.
Reduces the on-chip area occupied by voltage regulators due to lower maximum current ratings.
Minimizes reconfiguration of the power delivery network, thereby reducing switching losses and system complexity.
Provides robust and reliable power delivery with dynamic, real-time adaptation to workload currents, preventing system failure or stalling due to insufficient current supply.
Enables faster and more efficient dynamic voltage and frequency scaling (DVFS) due to the point-of-load regulation and minimized power supply noise.
Reduces I/O pin count devoted to power and ground signals.
Documented Applications
Real-time workload scheduling and energy-efficient task assignment in homogeneous and heterogeneous multi-core processor systems with under-provisioned on-chip voltage regulators.
Dynamic power management in chip multi-processors (CMPs) for applications requiring robust load balancing and energy optimization, including those running real-time, periodic, and benchmark workloads like SPEC CPU 2000 and SPEC CPU 2006.
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