Secure logic chip for resisting hardware trojan induced leakage in combinational logic
Inventors
Shi, Yiyu • SCHULZE, TRAVIS • KWIAT, KEVIN • KAMHOUA, CHARLES
Assignees
United States Department of the Air Force
Publication Number
US-11354452-B2
Publication Date
2022-06-07
Expiration Date
2036-09-29
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Abstract
The invention is a secure logic chip with resistance to hardware Trojan induced data leakage. The invention solves the untrustworthy fabrication risk problem by introducing a secure logic chip design such that even when the design is entirely known to an attacker and a data leakage Trojan is injected subsequently, no useful information can be obtained. This invention contains several features including randomized encoding of binary logic, converting any combinational binary logic into one with randomized encoding, and partitioning a randomized encoded logic for split manufacturing.
Core Innovation
The invention is a secure logic chip design that resists data leakage caused by hardware Trojans inserted in combinational logic. It introduces a randomized encoding scheme for binary logic signals, converting conventional combinational logic into a form with randomized dual-rail encoding. This encoding uses random logic values to mask true logic bits, making it infeasible for an attacker who knows the design or has procured fabricated chips to obtain useful information even after Trojan insertion.
The invention addresses the problem that arises from untrustworthy outsourced chip fabrication, where manufacturers may insert hardware Trojans that produce data leakage without altering normal chip behavior, thus evading standard detection methods like runtime monitoring and post-silicon testing. Since attackers can reverse-engineer designs from fabricated chips, traditional design-for-security approaches (obfuscation, camouflaging, split manufacturing) are insufficient to prevent leakage once the design is known. This patent advances a method and apparatus that secure the information by hiding the data using randomized encoding and securing the random signals via a partitioned chip implementation.
The design includes a secure input/output area fabricated separately and joined via quilt packaging, containing a random number generator, encoding and decoding logic gates (such as XOR gates), and multiplexers. Input signals are encoded with random bits before entering the unsecure external logic blocks, with outputs decoded similarly to recover true logic values. Multiple logic blocks with inverters are used to further increase complexity and reduce attack success probability by enlarging the search space for guessing the random values. Overall, this approach prevents hardware Trojans from successfully extracting meaningful data despite knowledge of the design or multiple fabrication runs.
Claims Coverage
The patent claims cover a secure logic chip structure combining secure and unsecure sections with specific components and logic encoding techniques. The main inventive features from the independent claims involve a secure input/output area with randomized encoding and decoding using logic gates and multiplexers, and a partitioning scheme using quilt packaging with multiple logic blocks that differ by at least one inverter.
Secure logic chip with partitioned secure input/output area
The secure logic chip comprises a secure section and an unsecure section. The secure section is fabricated with measures to prevent malicious intrusion and includes an input/output area that communicates with the unsecure external logic area. This input/output area contains a random number generator providing a random rail signal, first and second logic gates for encoding and decoding, and a multiplexer to select encoded outputs. The input signals are encoded with the random logic value before entering the unsecure area, and decoded using the random value after processing.
Use of XOR gates as encoding and decoding logic
In the secure input/output section, the first logic gate encodes the selected single rail input signal with the secure random logic value, and the second logic gate decodes the selected encoded output received from the unsecure area using the same random logic value. Both gates are specified as XOR gates to perform these encoding and decoding functions.
Multiple logic blocks in unsecure area with intentional inverter difference
The external unsecure area contains at least two logic blocks communicating with the encoding logic and multiplexer, where the first logic block includes an inverter along a rail that differs from the second logic block. This difference ensures the logic blocks are not identical, increasing complexity for attackers attempting to deduce random values.
The claims establish a secure logic chip architecture that leverages randomized encoding via XOR gates and multiplexers in a separately fabricated secure input/output area. The unsecure logic blocks include intentional inverter differences to maximize attack resistance, all integrated using quilt packaging to effectively prevent hardware Trojan induced data leakage.
Stated Advantages
Prevents hardware Trojans from extracting useful data even when the complete design is known or procured, by randomizing and encoding logic signals.
Separates and secures the random encoding signals and final multiplexers via secure fabrication and quilt packaging, prohibiting direct observation of critical signals.
Reduces overhead by allowing conversion of conventional logic to randomized dual-rail logic with manageable area and power increase.
Improves resistance against attackers by deploying multiple logic blocks with at least one inverter difference, exponentially increasing the guessing space for the random logic value.
Allows pre-fabrication of input/output modules as standardized circuits for reuse in multiple designs, streamlining secure fabrication.
Documented Applications
Securing combinational logic in semiconductor chips against data leakage caused by hardware Trojans.
Protecting sensitive designs fabricated in untrusted foundries or outsourced manufacturing processes.
Integration of secure input/output modules fabricated separately and combined via quilt packaging in chip design.
Military and aerospace defense platforms requiring high assurance from hardware Trojan insertion and data leakage.
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