Secure logic chip for resisting hardware trojan induced leakage in combinational logics
Inventors
Shi, Yiyu • SCHULZE, TRAVIS • KWIAT, KEVIN • KAMHOUA, CHARLES
Assignees
United States Department of the Air Force
Publication Number
US-11354451-B2
Publication Date
2022-06-07
Expiration Date
2036-09-29
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Abstract
The invention is a secure logic chip with resistance to hardware Trojan induced data leakage. The invention solves the untrustworthy fabrication risk problem by introducing a secure logic chip design such that even when the design is entirely known to an attacker and a data leakage Trojan is injected subsequently, no useful information can be obtained. This invention contains several features including randomized encoding of binary logic, converting any combinational binary logic into one with randomized encoding, and partitioning a randomized encoded logic for split manufacturing.
Core Innovation
The invention is a secure logic chip designed to resist data leakage caused by hardware Trojans, specifically in combinational logics. It introduces a secure logic chip design where the entire design may be known to an attacker, yet even if a data leakage Trojan is injected, no useful information can be obtained. This is achieved by employing randomized encoding of binary logic, converting any combinational binary logic into one with randomized encoding, and partitioning randomized encoded logic for split manufacturing.
The background of the invention identifies the problem of untrustworthy semiconductor fabrication arising from outsourcing chip manufacturing to potentially unsecure facilities. These situations allow attackers to insert hardware Trojans—malicious modifications to circuitry—without affecting normal chip operation while enabling data leakage through side channels. Existing countermeasures like runtime monitoring, post-silicon testing, and design for security aimed at detecting or obfuscating Trojans are insufficient, particularly when designs undergo multiple fabrication runs and attackers can reverse-engineer chips to inject Trojans in subsequent runs.
To address these challenges, the invention proposes a method using randomized dual-rail encoding where each binary logic value is encoded with multiple possible codes using a random rail generated by a random number generator. This random rail value protects information by making signals indecipherable if the random value is unknown. The design converts conventional Boolean functions to randomized dual-rail logic implemented through multiple logic blocks differing by inverters and a multiplexer controlled by the random rail. Additionally, the design partitions the chip so that the input/output area containing the random number generator, XOR encoding/decoding gates, and multiplexers are fabricated securely and joined to the main logic using Quilt Packaging, thus hiding the random rail and protecting against data leakage Trojans.
Claims Coverage
The patent contains one independent claim describing the secure logic chip's architecture and functional components. The main inventive features address secure partitioning of logic, randomized encoding and decoding with a random logic value, and integration using quilt packaging.
Secure partitioning with secure and unsecure sections
The chip comprises an unsecure section containing external logic blocks and a secure section inaccessible to malicious intrusion through secure fabrication. The secure section contains an input/output area that communicates with the unsecure section and includes a random number generator, random rail, logic gates, and a multiplexer.
Randomized encoding and decoding using a random logic value
A random number generator outputs a secure random logic value along the random rail that interfaces with first and second logic gates. The first logic gate encodes a selected single rail input with the random logic value to produce a secured dual-rail representation as input to the external area. The second logic gate decodes a dual-rail signal selected by the multiplexer from the external area with the random logic value to produce a secured single rail output.
Integration of secure input/output area via quilt packaging
The input/output area containing the random number generator, logic gates, and multiplexer is integrated within the secure logic chip by secure fabrication employing quilt packaging technology, allowing separate fabrication and secure joining of chip areas.
Use of multiple logic blocks with differing inverters
The external area includes at least two logic blocks communicating with the first logic gate and multiplexer, where each logic block contains at least one inverter arranged so that the logic blocks are not identical, enhancing security by complicating attacker guessing of random logic bits.
The independent claim covers a secure logic chip architecture employing randomized dual-rail encoding and decoding driven by a random logic value, secure fabrication partitioning using quilt packaging, and the use of multiple logic blocks with inverters to resist hardware Trojan induced data leakage.
Stated Advantages
Provides resistance to hardware Trojan induced data leakage even when the chip design is fully known to an attacker.
Separates and hides the random logic value and decoding circuitry in a securely fabricated input/output section, preventing attackers from decoding obtained information from compromised chip portions.
Introduces a randomized dual-rail encoding scheme that enlarges the guess space for attackers, making successful guessing of random logic values computationally prohibitive.
Allows design partitioning and secure integration via Quilt Packaging, enabling small secure I/O chips fabricated in trusted facilities to combine with larger outsourced chip portions, enhancing overall chip security.
Documented Applications
Protecting combinational logic chips against data leakage induced by hardware Trojans.
Implementation in security-critical systems such as military aerospace and defense platforms where hardware Trojan risks are especially critical.
Use of secure input/output chip modules fabricated separately for universal application in different designs via quilt packaging.
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