Dual dynamic random (DDR) access memory interface design for aerospace printed circuit boards
Inventors
Petrick, David J. • GEIST, ALESSANDRO D. • Flatley, Thomas P.
Assignees
National Aeronautics and Space Administration NASA
Publication Number
US-11109485-B1
Publication Date
2021-08-31
Expiration Date
2038-09-26
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Abstract
The present invention relates to a single board computer system with an improved memory and layout. The unique layout of the printed circuit board of the present invention allows for different parts to be placed in a back-to-back configuration to minimize the dimensions of the printed circuit board. This includes a high-performance radiation-hardened reconfigurable FPGA, for processing computation-intensive space systems, disposed on both sides of the printed circuit board. Four dual double data rate synchronous dynamic random-access memories (DDR2 SDRAMs) disposed on both the top side and on the bottom side of the printed circuit board reduce an operating voltage of said printed circuit board. A layout stack-up of the printed circuit board includes twenty-two symmetrical layers including ten ground layers, four power layers, six signal layers, a top layer, and a bottom layer.
Core Innovation
The present invention relates to an improved memory design and layout for a radiation-hardened single board computer system, useful for space applications. The invention features a printed circuit board that allows for different parts to be placed in a back-to-back configuration to minimize the dimensions of the printed circuit board. This includes a high-performance radiation-hardened reconfigurable FPGA disposed on both sides of the printed circuit board and four dual double data rate synchronous dynamic random-access memories (DDR2 SDRAMs) disposed on both the top side and the bottom side of the board.
The printed circuit board stack-up layout includes twenty-two symmetrical layers arranged in a two-halves configuration above and below a central plane of the printed circuit board. The layers comprise ten ground layers, four power layers, six signal layers, a top layer, and a bottom layer, enabling efficient power distribution and signal integrity. The unique layout supports placing parts back-to-back, reducing the printed circuit board size while also reducing the operating voltage through the use of DDR2 SDRAMs.
The problem being solved is the obsolescence and end of life of existing DDR1 SDRAM memories used in current space applications. Existing printed circuit boards for space use slower memory technologies with outdated interface signals, pinouts, and voltage requirements, which complicates upgrading and redesigning for newer technologies like DDR2 SDRAMs. The invention addresses the need for improved memory systems that provide higher memory throughput, reduced power consumption, and flexible integration into space-grade printed circuit boards to handle increasing data processing demands in space instruments, especially image processing.
Claims Coverage
The claims include one independent claim covering a radiation-hardened single board computer system with a distinct printed circuit board layout and memory configuration. This system incorporates specific stack-up layers and peripheral components to enable enhanced space-grade computing performance.
Radiation-hardened FPGA processors on both sides of the PCB
The system includes a first radiation tolerant FPGA processor device on the top side and a second radiation tolerant FPGA on the bottom side of the printed circuit board, enabling high-performance computing in a compact layout.
Symmetrical two-halves PCB stack-up with multiple layers
The printed circuit board includes a plurality of layers arranged symmetrically around a central plane in a two-halves configuration, comprising at least twenty-two symmetrical layers including ten ground layers, four power layers, six signal layers, a top layer, and a bottom layer, supporting signal integrity and power distribution.
Eight DDR2 SDRAM memories arranged top and bottom sides
Four DDR2 SDRAMs are disposed on the top side and four DDR2 SDRAMs on the bottom side mirroring the top, collectively storing operating system and dynamic application data, providing increased bandwidth and reduced operating voltage.
Peripheral components distributed on top and bottom sides
Peripheral components such as flash memory devices, programmable read only memory devices, voltage regulators including Buck Converters, multiplexers, and additional FPGAs with internal error correction are mounted on both sides of the printed circuit board to enhance functionality and control.
The independent claim defines a radiation-hardened single board computer system with a unique multi-layer symmetrical printed circuit board, dual FPGA processors on opposite sides, mirrored DDR2 SDRAM memory modules for operating system and application data storage, and a complementary set of peripheral components and power management that together enable advanced space-grade processing capabilities with reduced power and size.
Stated Advantages
The use of DDR2 SDRAMs reduces the operating voltage from 2.5V to 1.8V, reducing power consumption and thermal load.
The back-to-back component configuration minimizes the physical dimensions of the printed circuit board, enabling a smaller, compact system.
Shared address/clock/command/control lines across paired DDR2 SDRAMs reduce FPGA input/output pin usage, increasing flexibility.
The symmetrical multi-layer PCB stack-up improves signal integrity and power distribution, supporting high-performance radiation-hardened computing.
Increased memory throughput provides more than twice the speed of previous designs, enhancing support for next-generation space instruments.
Documented Applications
Use in space applications such as very small miniaturized systems like the SpaceCube 2.0™ processor card for robotic arms, international space station payloads, and satellites used in space research.
Systems employed in small free flyer satellites, balloons, sounding rockets, unmanned aerial vehicles (UAVs), and small instruments requiring high-end data processing.
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