Power savings in processors
Inventors
Cherupalli, Hari • Kumar, Rakesh • Sartori, John
Assignees
University of Illinois at Urbana Champaign • University of Minnesota System • University of Illinois System
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Publication Number
US-10866630-B2
Publication Date
2020-12-15
Expiration Date
Abstract
A method includes generating gate-level activity information of a processor design for all possible executions of a target application for any possible inputs to the target application. The method includes performing a constrained timing analysis on the processor design based on the gate-level activity information to determine a minimum operating voltage for executing the target application on the processor.
Core Innovation
The invention generates gate-level activity information for a software-programmable processor design across all possible executions of a target application for any possible inputs, including identifying parts of the processor design that are not exercised by the target application. This gate-level activity information is used to determine peak power and energy for executing the target application on the processor.
Peak power and energy determination is based on constrained worst-case timing analysis and on execution-structure representations derived from the gate-level activity information, including generating an execution tree and concatenating execution paths into a single execution trace. The approach also determines peak power using a peak power trace formed by generating even cycles power traces and odd cycles power traces and interleaving power values, followed by selecting a maximum per cycle power value.
The invention further groups gates into module-oblivious power domains based on the gate-level activity information, where each domain includes an arbitrary set of gates having correlated activity. The target application is modified to direct each module-oblivious power domain when to turn off and on, including handling wake-up latency so domains are activated N cycles before a period of activity.
Claims Coverage
The document contains three independent claims. Across these claims, the inventive features cover generation of gate-level activity information for all possible executions and inputs, determination of peak power and energy from that gate-level activity, an execution tree and single execution trace with even/odd cycle interleaving, and module-oblivious power domains with target-application control of on/off behavior.
Generating gate-level activity for all possible executions and identifying unexercised parts
Generating, via a processing system, gate-level activity information of a software-programmable processor design for all possible executions of a target application for any possible inputs to the target application to identify parts of the processor design that are not exercised by the target application.
Determining peak power and energy based on gate-level activity
Determining, via the processing system, peak power and energy of the processor design based on the gate-level activity information for executing the target application on the processor, wherein the determined peak power for executing the target application on the processor is less than a rated peak power of the processor design.
Generating an execution tree and single execution trace for peak power and energy
Generating an execution tree based on the gate-level activity information; concatenating execution paths in the execution tree into a single execution trace; and determining the peak power based on the single execution trace, wherein determining the peak power and energy comprises these actions.
Peak power determination via even/odd cycle power traces and interleaving
Generating an even cycles power trace; generating an odd cycles power trace; generating a peak power trace by interleaving power values from the even cycles in the even power trace and the odd cycles in the odd cycles power trace; and determining the peak power based on a maximum per cycle power value in the peak power trace.
Grouping gates into module-oblivious power domains
Grouping, via the processing system, gates of the processor design into a plurality of module-oblivious power domains based on the gate-level activity information, each of the plurality of module-oblivious power domains comprising an arbitrary set of gates having correlated activity.
Modifying the target application for module-oblivious power domain turn off/on
Modifying, via the processing system, the target application to direct each of the plurality of module-oblivious power domains when to turn off and on.
Together, the independent claims require generation of gate-level activity information across all possible executions and inputs, determination of peak power and energy from that gate-level activity, an even/odd cycle interleaving approach for peak power, and grouping gates into module-oblivious power domains with control of power-domain on/off behavior.
Stated Advantages
The determined peak power for executing the target application is less than a rated peak power of the processor design.
Documented Applications
Sizing an energy harvester or energy storage device for the processor based on the determined peak power and energy.
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