Method and system for inter-thread communication using processor messaging

Inventors

Dice, David • Moir, Mark S.

Assignees

Oracle America Inc

Abstract

In shared-memory computer systems, threads may communicate with one another using shared memory. A receiving thread may poll a message target location repeatedly to detect the delivery of a message. Such polling may cause excessive cache coherency traffic and/or congestion on various system buses and/or other interconnects. A method for inter-processor communication may reduce such bus traffic by reducing the number of reads performed and/or the number of cache coherency messages necessary to pass messages. The method may include a thread reading the value of a message target location once, and determining that this value has been modified by detecting inter-processor messages, such as cache coherence messages, indicative of such modification. In systems that support transactional memory, a thread may use transactional memory primitives to detect the cache coherence messages. This may be done by starting a transaction, reading the target memory location, and spinning until the transaction is aborted.

Core Innovation

The disclosed approach reduces inter-thread and shared-memory polling overhead in a multithreaded computer system by detecting updates to a shared memory location using inter-processor messages instead of spinning on the shared variable. In a transactional memory system, a given thread executes as part of a transaction and reads a value from a shared memory location shared by another thread executing on a different processor. The shared memory location represents a lock and the value represents a value of the lock.

After reading, the given thread begins execution of a sequence of program instructions as part of the transaction. While executing the sequence, the given processor receives an inter-processor message from the different processor indicating that a value has been written to the shared memory location. The indication that the value has been written indicates that the other thread has released the lock.

In response to receiving the inter-processor message, the method aborts the transaction, where aborting the transaction terminates execution of the sequence of instructions. Subsequent to receiving the inter-processor message, the given thread attempts to acquire the lock, with the overall result being lock release detection driven by cache coherence and inter-processor messaging. The disclosure also includes using hardware performance counters to detect and/or base an indication on cache coherence messages, and applying the approach to lock acquisition by treating the lock variable as the shared memory location.

Claims Coverage

The partial document includes three independent claims covering a method, a system, and a non-transitory computer readable storage medium. Across these independent claims, a common set of inventive features is present: transactional reading of a lock value from a shared memory location across processors, inter-processor message reception indicating a value write to the lock location, transaction abort terminating the in-transaction instruction sequence, and subsequent lock acquisition attempt.

Across the method, system, and storage-medium independent claims, the central claimed coverage is transactional lock handling across multiple processors where inter-processor messages indicating a write to the shared lock location cause an abort that terminates the transactional instruction sequence, followed by an attempt to acquire the lock.

Stated Advantages

Documented Applications