Dual dynamic random (DDR) access memory interface design for aerospace printed circuit boards
Inventors
Petrick, David J. • GEIST, ALESSANDRO D. • Flatley, Thomas P.
Assignees
National Aeronautics and Space Administration NASA
Publication Number
US-10667398-B1
Publication Date
2020-05-26
Expiration Date
2038-09-26
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Abstract
The present invention relates to a single board computer system with an improved memory and layout. The unique layout of the printed circuit board of the present invention allows for different parts to be placed in a back-to-back configuration to minimize the dimensions of the printed circuit board. This includes a high-performance radiation-hardened reconfigurable FPGA, for processing computation-intensive space systems, disposed on both sides of the printed circuit board. Four dual double data rate synchronous dynamic random-access memories (DDR2 SDRAMs) disposed on both the top side and on the bottom side of the printed circuit board reduce an operating voltage of said printed circuit board. A layout stack-up of the printed circuit board includes twenty-two symmetrical layers including ten ground layers, four power layers, six signal layers, a top layer, and a bottom layer.
Core Innovation
The present invention relates to an improved memory design and layout for a radiation-hardened single board computer system, which is useful for space applications. It features a unique printed circuit board layout allowing different parts to be placed in a back-to-back configuration to minimize the dimensions of the printed circuit board. This design includes a high-performance radiation-hardened reconfigurable FPGA disposed on both sides of the printed circuit board to process computation-intensive tasks in space systems.
The printed circuit board includes four dual double data rate synchronous dynamic random-access memories (DDR2 SDRAMs) on both the top side and bottom side, which reduce the operating voltage of said board. The layout stack-up comprises twenty-two symmetrical layers including ten ground layers, four power layers, six signal layers, a top layer, and a bottom layer. The improvement supports significant data processing capability with radiation-tolerant parts, achieving at least 3,000 MIPS, over ten times the performance of comparable space processors.
The problem being addressed is that previous DDR1 SDRAM memories used in space applications are outdated, no longer appropriate or available, and the memory systems are too slow for many space instruments. Upgrading to newer DDR memory technologies requires different interface signals, pinouts, and voltage requirements that complicate printed circuit board layouts. This invention redesigns the memory system and layout to accommodate DDR2 SDRAMs, providing greater memory throughput and supporting next-generation instruments in space applications.
Claims Coverage
The patent includes three principal independent claims covering the radiation-hardened single board computer system and its multi-layer printed circuit board design.
Radiation-hardened single board computer system with a symmetrical multi-layer PCB stack-up
A printed circuit board with top and bottom sides arranged symmetrically in a two-halves configuration about a central plane, mounting FPGA processor devices on both sides, with at least one top-side connector and multiple peripheral components. The top side includes a specific stack-up of ground, signal, power layers and a top layer, arranged upward from the central plane in an alternating and layered manner.
Symmetrical bottom side stack-up layout of the PCB
The bottom side of the PCB has a defined stack-up from the center plane outward comprising ground layers, signal layers, power layers, and a bottom layer arranged similarly symmetrically to the top side but mirrored and layered to support the dual FPGA arrangement and peripheral components.
Multi-layer printed circuit board configured for a single radiation-hardened processing system with specific layering and back-to-back arrangement
A PCB including a top half and bottom half separated by a central plane, arranged symmetrically with four ground layers and three signal layers alternately disposed on each half, with pairs of power layers below the top and bottom layers plus additional ground layers between power and outer layers. The top and bottom layers include multiple land pads for connecting electronic components. The board supports back-to-back mounting of column grid array devices and uses blind and through vias to connect pins in a back-to-back configuration, with FPGA processors and peripheral components mounted on both sides, and at least one top-side connector.
The claims collectively cover a radiation-hardened single board computer system utilizing a multi-layer, symmetric printed circuit board design with a specific layer stack-up and back-to-back FPGA and DDR2 SDRAM memory placement to enhance space application performance and durability.
Stated Advantages
The DDR2 SDRAM memories reduce operating voltage from 2.5V to 1.8V, lowering power consumption and thermal load.
The unique back-to-back PCB layout minimizes the printed circuit board dimensions, facilitating compact, small-sized system designs.
Sharing address, clock, command, and control lines among paired DDR2 SDRAMs reduces FPGA I/O usage, increasing system flexibility.
The system achieves high processing capability of at least 3,000 MIPS, more than ten times other comparable space processors.
Radiation-hardened parts and redundant data storage improve radiation mitigation for space applications.
Documented Applications
The single board computer system is used in space applications such as small miniaturized systems for robotic arms, International Space Station payloads, or satellites for space research.
Other applications include small free flyer satellite systems, balloons, sounding rockets, unmanned aerial vehicles (UAVs), and small instruments requiring high-end data processing in space environments.
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