Post design integrated circuit manufacturing obfuscation

Inventors

Levine, Neal • Gahoonia, Aman • Lloyd, Jon • Pentrack, David W.

Assignees

United States Department of the Army

Abstract

An integrated circuit includes a plurality of vertically-stacked layers including a front end of line (FEOL) layer and a back end of line (BEOL) layer. The FEOL layer includes individual transistors that are not interconnected. The BEOL layer includes transistor interconnections and no transistors. The transistors are electrically connected to the transistor interconnections by vias within the FEOL ad BEOL layers. The FEOL and BEOL layers each have contact pads on the top and bottom surfaces thereof that are each in alignment with vias, are arranged in a checkerboard pattern, and occupy about fifty percent of the surface area of the FEOL and BEOL layers. The contact pads on a top surface of the FEOL layer are in electrical communication with contact pads on a bottom surface of the BEOL layer to facilitate vertical current flow between the transistors and the transistor interconnections through the vias.

Core Innovation

The invention relates to a method and integrated circuit design aimed at mitigating the risk of intellectual property theft during integrated circuit manufacturing. It involves partitioning an integrated circuit design layout file into multiple design files that separate front-end-of-line (FEOL) sub-circuits containing transistors from back-end-of-line (BEOL) sub-circuits containing transistor interconnections. These sub-circuits are fabricated separately in different foundries on individual substrates and then vertically stacked, so no single foundry has access to the complete circuit functionality information.

The problem solved is the vulnerability of integrated circuit intellectual property during manufacturing, particularly the threat posed by the manufacturing foundry which might not be fully vetted. Traditional obfuscation and staff vetting techniques are insufficient due to the increasing sophistication of adversaries and human error risks. This invention effectively prevents any one manufacturing entity from deducing the overall circuit function or misappropriating the intellectual property, by structurally partitioning the design and outsourcing fabrication to multiple foundries.

The innovation preserves the typical vertical architecture of integrated circuits by having the FEOL layer contain unconnected transistors and the BEOL layers contain transistor interconnections without transistor structures. The layers have contact pads arranged in a checkerboard pattern covering about fifty percent of the surface to enable vertical electrical connections via aligned vias. This design allows vertical current flow between transistors and interconnections while maintaining the separation of functional information, and does not require the original circuit designer to alter the basic design process.

Claims Coverage

The patent contains one independent claim describing a three-dimensional integrated circuit with specific layered structural features.

These inventive features collectively define a vertically stacked integrated circuit structure with separated transistor and interconnect layers, connected through a specifically arranged pattern of vias and contact pads facilitating vertical electrical connections, thereby enabling the manufacturing obfuscation technique.

Stated Advantages

Documented Applications