Bioinformatics systems, apparatuses, and methods executed on an integrated circuit processing platform
Inventors
Van Rooyen, Pieter • Ruehle, Michael • McMillen, Robert J.
Assignees
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Publication Number
US-10210308-B2
Publication Date
2019-02-19
Expiration Date
Abstract
A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes a structured ASIC formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the structured ASIC connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits are arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the sequence analysis pipeline on the reads of genomic data. Each subset of the hardwired digital logic circuits is formed in a wired configuration to perform the one or more steps in the sequence analysis pipeline.
Core Innovation
The invention relates to executing a sequence analysis pipeline for genomic data using a set of hardwired digital logic circuits interconnected by physical electrical interconnects and arranged as a set of processing engines. The pipeline operates on a plurality of reads of genomic data of a subject together with one or more genetic reference sequences and an index of the one or more genetic reference sequences. At least one processing engine performs mapping by accessing from memory a selected read and mapping the selected read to one or more segments of the genetic reference sequences based on the index to produce a mapped read.
An alignment module accesses from memory the one or more genetic reference sequences and the selected mapped read, and aligns the selected read to one or more positions in the one or more segments of the genetic reference sequences to produce an aligned read comprising a sequence of nucleotides. Result data from the alignment module is communicated through an output associated with one or more of the physical electrical interconnects. The same overall sequence analysis pipeline structure is extended to variant calling that compares nucleotides in a mapped read to nucleotides in genetic reference sequences to determine one or more differences and generate one or more variant calls representing the differences.
A related aspect discloses a genomics analysis platform that includes one or more first integrated circuits responsive to basecalling software algorithms and one or more second integrated circuits configured by firmware to arrange sets of hardwired digital logic circuits as processing engines. The second integrated circuits perform one or more mapping, aligning, and/or variant calling steps in the sequence analysis pipeline, and the platform includes shared memory electronically connected with each CPU or GPU and each second integrated circuit to provide genetic sequence data and to store result data from genomic processing steps.
Claims Coverage
The independent claims are clm-00001, clm-00008, clm-00013, and clm-00016. Across these claims, the coverage includes four inventive features: mapping and alignment in hardwired processing engines, mapping followed by variant calling, CPU/GPU basecalling with second integrated circuits and shared memory, and an FPGA with wired interconnections forming processing engines including base calling, mapping, alignment, sorting, and variant calling.
Hardwired processing engines for sequence analysis pipeline with mapping and alignment
A set of hardwired digital logic circuits interconnected by physical electrical interconnects arranged as processing engines, including a mapping module that accesses from memory an index to map a selected read to one or more segments to produce a mapped read and an alignment module that accesses from memory reference sequences and the mapped read to align the selected read to one or more positions to produce an aligned read, with output communicating alignment result data.
Mapping followed by variant calling on mapped read compared to genetic reference
A mapping module configured to access from memory, according to nucleotides in a selected read, the index to map the selected read to one or more segments and produce a mapped read, and a variant calling module configured to access in memory the mapped read and at least one genetic reference sequence, compare nucleotides to determine one or more differences, and generate variant calls representing the differences, with output communicating variant calling result data.
CPU/GPU basecalling with second integrated circuits as hardwired mapping, aligning, and variant calling engines using shared memory
A genomics analysis platform having one or more first integrated circuits (CPU or GPU) responsive to basecalling software algorithms to instruct a first set of basecalling operations, one or more second integrated circuits configured by firmware to arrange hardwired digital logic circuits as processing engines to perform one or more mapping, aligning, and/or variant calling steps, and shared memory electronically connected with each CPU or GPU and each second integrated circuit to provide genetic sequence data and store result data.
FPGA with wired interconnections forming processing engines including base calling, mapping, alignment, sorting, and variant calling
An FPGA comprising a plurality of digital logic circuits with wired connections arranged to interconnect and configure a first subset of the plurality of digital logic circuits to form processing engines including a base calling engine, a mapping engine, an alignment engine, a sorting engine, and a variant calling engine, where at least some processing engines are at least partially reconfigurable by the wired connections and operate using stored genetic reference sequences and an index.
The independent claims collectively define a hardware-accelerated sequence analysis pipeline that uses an index of genetic reference sequences for mapping and, in some claims, alignment and/or variant calling implemented via hardwired digital logic circuits arranged as processing engines, with memory interfacing and, in a broader platform claim, CPU/GPU basecalling integrated with second integrated circuits and shared memory.
Stated Advantages
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