Apparatus, method and article of manufacture for partially resisting hardware trojan induced data leakage in sequential logics
Inventors
KWIAT, KEVIN • KAMHOUA, CHARLES • NJILLA, LAURENT • Shi, Yiyu • SCHULZE, TRAVIS
Assignees
United States Department of the Air Force
Publication Number
US-10121011-B2
Publication Date
2018-11-06
Expiration Date
2037-01-03
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Abstract
Apparatus, method and article of manufacture providing a randomized encoding scheme for sequential logics, for resistance to data leakage. Invention employs dual-rail encoding to randomize the information in the chip, and employs three-dimensional integration technology to protect the critical information that is needed to decode the data anywhere on-chip. With the present invention, even when the entire design is completely known to the attacker who also has full access to the outsourced portion, it is still not always possible to identify the information in the chip using data leakage Trojans.
Core Innovation
The invention provides an apparatus, method, and article of manufacture that employs a randomized encoding scheme for sequential logics to resist data leakage caused by hardware Trojans. It utilizes dual-rail encoding to randomize the information processed within the chip, combined with three-dimensional integration technology to protect the critical information required to decode the data anywhere on-chip. The invention ensures that even if the entire design is known to an attacker who has full access to the outsourced fabrication portion, it remains not always possible to identify the information through data leakage Trojans.
The invention addresses the problem arising from untrustworthy semiconductor fabrication facilities where malicious hardware, known as hardware Trojans, can be inserted during manufacturing. In particular, data leakage Trojans that capture processed data are difficult to detect as they maintain original chip functionality and result in negligible area or power increase. Current design-for-security methods such as logic obfuscation, layout camouflaging, and split manufacturing attempt to make designs harder to interpret but can be compromised when designs undergo multiple fabrication runs and attackers reverse-engineer procured chips to create targeted Trojans.
This invention provides a novel circuit-level design technique that partially resists data leakage Trojans by randomizing binary logic encoding and partitioning randomized encoded logic for split manufacturing and three-dimensional integration. The design uses at least two random logic state generators to encode inputs and multiplex outputs of combinational logic according to the random states. The random rails are protected on a separate chip layer fabricated securely and stacked with the logic portion, hindering attackers from access and reducing effective data leakage even if Trojans are injected post-manufacture.
Claims Coverage
The patent contains three independent claims that cover the apparatus, method, and secure logic chip as an article of manufacture implementing randomized encoding for sequential logic to resist data leakage hardware Trojans.
Randomized encoding of sequential logic inputs with random logic state generators
The apparatus comprises at least two combinational logic circuit functions each with outputs and input pairs, and at least two random logic state generators outputting random logic states. Each logic input is encoded using a Boolean operation on a preselected random logic state. A multiplexer selects among combinational logic outputs according to the random logic states.
Selective multiplexing, latching, and decoding using exclusive OR operation tied to current and prior random logic states
The apparatus uses a latch connecting to the multiplexer output, and an exclusive OR circuit to decode the output, where the second input is encoded by a Boolean operation on the current and prior clock cycle states of the preselected random logic state. The method covers corresponding steps involving generation of random logic states, encoding inputs, multiplexing, latching, and exclusive OR decoding based on current and prior random states.
Three-dimensional integrated secure logic chip partitioned into logic and security portions with through-silicon-vias
The secure logic chip includes a logic portion with combinational circuits and a security portion comprising random logic state generators, multiplexers controlled by random logic states, latches, and exclusive OR circuits to decode outputs as functions of random states. The two portions are manufactured separately, arranged as a physical stack, and electrically connected via through-silicon-vias, protecting random rails and registers from compromised fabrication.
The independent claims cover a randomized dual-rail encoding scheme implemented in apparatus, method, and secure chip form. They include the use of dual random state generators, selective multiplexing based on these states, encoding inputs, latching outputs, and decoding via exclusive OR operation using current and prior random states. They emphasize three-dimensional integration techniques to isolate security-related components from untrusted fabrication, thereby resisting data leakage from hardware Trojans.
Stated Advantages
Provides partial resistance to hardware Trojan induced data leakage even when the design is fully known and accessible by attackers.
Randomizes information in the chip via dual-rail encoding to prevent easy identification of critical data by data leakage Trojans.
Employs three-dimensional integration technology to protect critical decoding information physically by placing random number generators and control registers in a securely fabricated chip layer separated from the potentially untrusted logic chip.
Enables design methods that reduce side-channel leakage susceptibility even after data leakage hardware Trojans have been injected post-design knowledge exposure.
Documented Applications
Resisting data leakage hardware Trojans inserted during semiconductor fabrication in untrustworthy fabrication facilities.
Securing sequential logic circuits in chip designs where multiple fabrication runs allow attackers to reverse-engineer chips and insert Trojans.
Using three-dimensional integrated chips with partitioned security and logic portions to protect random rails and encoding state information from attackers.
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